Design optimizations of a high performance microprocessor using combinations of dual-VT allocation and transistor sizing

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2002, Pages 218-219

  Tschanz, James ^a   Ye, Yibin ^a   Wei, Liqiong ^a   Govindarajulu, Venkatesh ^a   Borkar, Nitin ^a   Burns, Steven ^a   Karnik, Tanay ^a   Borkar, Shekhar ^a   De, Vivek ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; OPTIMIZATION; TRANSISTOR TRANSISTOR LOGIC CIRCUITS;

LEAKAGE POWER; MAXIMUM CLOCK FREQUENCY; MICROPROCESSOR DESIGNS;

MICROPROCESSOR CHIPS;

EID: 0242611625     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (1)

1. S. Tyagi et al., 2000 IEDM, pp. 567-570.