Differential CMOS edge-triggered flip-flop with clock-gating

Electronics Letters

Volumn 38, Issue 1, 2002, Pages 9-11

  Xia, Y ^a   Almaini, A E A ^a  

^a EDINBURGH NAPIER UNIVERSITY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC INVERTERS; ELECTRIC LOSSES; ESTIMATION; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; TRANSISTORS; TRIGGER CIRCUITS;

CLOCK-GATING; DIFFERENTIAL EDGE-TRIGGERED FLIP-FLOPS; POWER REDUCTION; SOFTWARE PACKAGE PSPICE;

TIMING CIRCUITS;

EID: 0037012115     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20020038     Document Type: Article

References (6)

1. A reduced clock saving flip-flop (RCSFF) for 63% power reduction
2. Low power flip-flop with clock gating on master and slave latches
3. 2MOS output latches
4. Differential CMOS edge-triggered flip-flop based on clock racing
5. Low power double edge-triggered flip-flop using one latch
6. Comparative analysis of masterslave latches and flip-flops for high-performance and low-power systems