Clock-gating and its application to low power design of sequential circuits

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

Volumn 47, Issue 3, 2000, Pages 415-420

  Wu, Qing ^a   Pedram, Massoud ^b   Wu, Xunwei ^a  

^a University of Southern California   (United States)

^b NINGBO UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POWER SUPPLIES TO APPARATUS; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; SEQUENTIAL CIRCUITS; TRIGGER CIRCUITS;

CLOCK GATING; MASTER CLOCK; POWER DISSIPATION; QUATERNARY VARIABLE;

TIMING CIRCUITS;

EID: 0034156657     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/81.841927     Document Type: Article

References (5)

1. M. PedramPower minimization in IC design: Principles and applications," ACM Trans. Design Automation, vol. 1, no. 1, pp. 3-56, Jan. 1996.
2. G. FriedmanClock distribution design in VLSI circuits: An overview," in Proc. IEEE ISCAS, San Jose, CA, May 1994, pp. 1475-1478.
3. E. Tellez, A. Farrah, and M. SarrafzadehActivity-driven clock design for low power circuits," in Proc. IEEEICCAD, San Jose, CA, Nov. 1995, pp. 62-65.
4. M. Alidina and J. Monteiro et al., "Precomputation-based sequential logic optimization for low power," IEEE Trans. VLSI Syst., vol. 2, pp. 426-436, Dec. 1994.
5. L. Benini and G. De MicheliSymbolic techniques of clock-gating logic for power optimization of control-oriented synchronous networks," in Proc. European Design Test Conf., Paris, France, 1997, pp. 514-520.