Exploiting an I-IP for In-field SOC test

IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2004, Pages 404-412

  Bernardi, P ^a   Rebaudengo, M ^a   Reorda, M Sonza ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CONTROL SCHEMA; INFRASTRUCTURE; MANUFACTURING TESTS; SYSTEM-ON-CHIP (SOC);

DATA STORAGE EQUIPMENT; LARGE SCALE SYSTEMS; MICROPROCESSOR CHIPS;

INTEGRATED CIRCUITS;

EID: 24944563988     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFTVS.2004.1347865     Document Type: Conference Paper

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