SCOPUS 정보 검색 플랫폼

IEEE Design and Test of Computers

Volumn 19, Issue 3, 2002, Pages 24-36

Embedded timing analysis: A SoC infrastructure

(2) Tabatabaei, Sassan b Ivanov, André a

a UNIVERSITY OF BRITISH COLUMBIA (Canada)

b Vector 12 Corp (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY LOCKED LOOPS; EMBEDDED TIME INTERVAL ANALYZER; EMBEDDED TIMING ANALYSIS; SYSTEM ON A CHIP; TIME TO DIGITAL CONVERTERS;

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DIGITAL CIRCUITS; ELECTRIC NETWORK ANALYSIS; FLIP FLOP CIRCUITS; JITTER; LOGIC GATES; OSCILLATORS (ELECTRONIC); PHASE LOCKED LOOPS; TIME DOMAIN ANALYSIS; TIMING CIRCUITS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036575437 PISSN: 07407475 EISSN: None Source Type: Journal
DOI: None Document Type: Article

Times cited : (60)

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