Infrastructure IP for configuration and test of boards and systems

IEEE Design and Test of Computers

Volumn 20, Issue 3, 2003, Pages 78-87

  Clark, C J ^a   Ricchetti, Mike ^a  

^a Intellitech Corp   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATION; FIELD PROGRAMMABLE GATE ARRAYS; FLIP FLOP CIRCUITS; MICROPROCESSOR CHIPS; OPTIMIZATION; SEMICONDUCTOR DEVICE MANUFACTURE;

MULTIBOARD SYSTEMS;

PRINTED CIRCUIT BOARDS;

EID: 0038382891     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2003.1198689     Document Type: Review

References (11)

1. Y. Zorian, "Guest Editor's Introduction: What is Infrastructure IP?" IEEE Design & Test of Computers, vol. 19, no. 3, May-June 2002, pp. 5-7.
2. "Can System Test and IC Test Learn from Each Other?" http://www.ecs.umass.edu/systest/pastevents.html.
3. C.J. Clark and Mike Ricchetti, "What's Wrong with My Current Configuration and Test Approach?" Intellitech application note, Intellitech Corp., 2003; http://www.intellitech.com/technologies/candt.asp.
4. "SN54ACT8997, SN74ACT8997: Scan Path Linkers with 4-Bit Identification Buses Scan-Controlled IEEE Std. 1149.1 (JTAG) TAP Concatenators," Texas Instruments, 1996; http://www-s.ti.com/sc/psheets/scas157d/scas157d.pdf.
5. "SCANPSC110F: Scan Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 Test Support)," Nat'l Semiconductor Corp., 1999; http://www.national.com/ds/SC/SCANPSC110F.pdf.
6. K.P. Parker and D. Zimmerle, "Boundary Scan Signals Future Age of Test," EP&P, July 2002; http://www.e-inslte.net/epp/lndex.asp?layout=article&articleld=CA231649.
7. M. Ricchetti, C.J. Clark, and B. Dervisoglu, Method and Apparatus for Providing Optimized Access to Circuits for Debug, Programming, and Test, Patent Cooperation Treaty (PCT) patent application W00171876, World Intellectual Property Organization, Geneva, 2000.
8. P. Forstner, "Test-Bus Controller SN74ACT8990," application report, Texas Instruments, 2000; http://www-s.ti.com/sc/psheets/scaa044/scaa044.pdf.
9. M. Ricchetti and C.J. Clark, Method and Apparatus for Embedded Built-in Self-Test (BIST) of Electronic Circuits and Systems, US patent application 10/142,556, US Patent and Trademark Office, Washington, D.C., 2001.
10. "SN54ABT8996, SN74ABT8996:10-Bit Addressable Scan Ports Multidrop-Addressable IEEE Std 1149.1 (JTAG) TAP Transceiver," data sheet, Texas Instruments, 1999; http://www-s.ti.com/sc/psheets/scbs489c/scbs489c.pdf.
11. C.J. Clark and M. Ricchetti, Method and Apparatus for Optimized Parallel Testing and Access of Electronic Circuits, PCT patent application WO03005050, World Intellectual Property Organization, Geneva, 2001.