-
1
-
-
0142206042
-
-
2001 edition
-
ITRS, 2001 edition, http://public.itrs.net/Files/2001ITRS/Home.htm
-
-
-
-
3
-
-
0032306939
-
Native Mode Functional Test Generation for Microprocessors with Applications to Self-Test and Design Validation
-
J.Shen, J.Abraham, "Native Mode Functional Test Generation for Microprocessors with Applications to Self-Test and Design Validation", in Proc. of the International Test Conference 1998, pp. 990-999.
-
(1998)
Proc. of the International Test Conference
, pp. 990-999
-
-
Shen, J.1
Abraham, J.2
-
5
-
-
84893681164
-
On the Test of Microprocessor IP Cores
-
Munich, Germany, March
-
F.Corno, M.Sonza Reorda, G.Squillero, M.Violante, "On the Test of Microprocessor IP Cores", in Proc. of the Design Automation & Test in Europe 2001, Munich, Germany, March 2001, pp.209-213
-
(2001)
Proc. of the Design Automation & Test in Europe 2001
, pp. 209-213
-
-
Corno, F.1
Reorda, M.S.2
Squillero, G.3
Violante, M.4
-
7
-
-
0030245490
-
Hierachical Test Generation Under Architectural Level Functional Constraints
-
Sept.
-
J. Lee, J.H. Patel, "Hierachical Test Generation Under Architectural Level Functional Constraints", in IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no. 9, Sept. 1996, pp. 1144-1151
-
(1996)
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems
, vol.15
, Issue.9
, pp. 1144-1151
-
-
Lee, J.1
Patel, J.H.2
-
8
-
-
0035272504
-
Software-Based Self-Testing Methodology for Processor Cores
-
March
-
Li Chen, S.Dey, "Software-Based Self-Testing Methodology for Processor Cores", IEEE Transactions on CAD of Integrated Circuits and Systems, vo.20, no.3, pp. 369-380, March 2001.
-
(2001)
IEEE Transactions on CAD of Integrated Circuits and Systems
, vol.20
, Issue.3
, pp. 369-380
-
-
Chen, L.1
Dey, S.2
-
9
-
-
0043195905
-
Instruction-Based Self-Testing of Processor Cores
-
N.Kranitis, D.Gizopoulos, A.Paschalis, Y.Zorian, "Instruction-Based Self-Testing of Processor Cores", in Proceedings of the IEEE VLSI Test Symposium 2002, pp. 223-228.
-
(2002)
Proceedings of the IEEE VLSI Test Symposium
, pp. 223-228
-
-
Kranitis, N.1
Gizopoulos, D.2
Paschalis, A.3
Zorian, Y.4
-
11
-
-
0036645652
-
Embedded Software-Based Self-Test for Programmable Core-Based Designs
-
July-August
-
A.Krstic, L.Chen, W.-C.Lai, K.-T.Cheng, S.Dey, "Embedded Software-Based Self-Test for Programmable Core-Based Designs", IEEE Design & Test of Computers, July-August 2002, pp. 18-26.
-
(2002)
IEEE Design & Test of Computers
, pp. 18-26
-
-
Krstic, A.1
Chen, L.2
Lai, W.-C.3
Cheng, K.-T.4
Dey, S.5
-
12
-
-
0035248749
-
Realization-Independent ATPG for Designs with Unimplemented Blocks'
-
February
-
H. Kim, J. Hayes, "Realization-Independent ATPG for Designs with Unimplemented Blocks'", IEEE Transactions on CAD of Integrated Circuits and Systems, vo.20, no.2, pp. 290-306, February 2001.
-
(2001)
IEEE Transactions on CAD of Integrated Circuits and Systems
, vol.20
, Issue.2
, pp. 290-306
-
-
Kim, H.1
Hayes, J.2
-
13
-
-
0000934719
-
An Effective BIST Architecture for Fast Multiplier Cores
-
A. Paschalis, D.Gizopoulos, N. Kranitis, M. Psarakis, Y. Zorian, "An Effective BIST Architecture for Fast Multiplier Cores", in Proc. of the Design Automation & Test in Europe 1999, pp.117-121
-
(1999)
Proc. of the Design Automation & Test in Europe
, pp. 117-121
-
-
Paschalis, A.1
Gizopoulos, D.2
Kranitis, N.3
Psarakis, M.4
Zorian, Y.5
-
14
-
-
0033350972
-
An Effective Built-In Self-Test Scheme for Parallel Multipliers
-
Sept. 99
-
D. Gizopoulos, A. Paschalis, Y. Zorian, "An Effective Built-In Self-Test Scheme for Parallel Multipliers", in IEEE Transactions on Computers, vol. 48, no.9, pp. 936-950, Sept. 99
-
IEEE Transactions on Computers
, vol.48
, Issue.9
, pp. 936-950
-
-
Gizopoulos, D.1
Paschalis, A.2
Zorian, Y.3
-
15
-
-
11844261646
-
-
Plasma CPU Model, http://www.opencores.org/projects/mips
-
Plasma CPU Model
-
-
|