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Volumn , Issue , 2003, Pages 431-440

Application and Analysis of RT-Level Software-Based Self-Testing for Embedded Processor Cores

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SOFTWARE; DESIGN FOR TESTABILITY;

EID: 0142246920     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (23)

References (16)
  • 1
    • 0142206042 scopus 로고    scopus 로고
    • 2001 edition
    • ITRS, 2001 edition, http://public.itrs.net/Files/2001ITRS/Home.htm
  • 3
    • 0032306939 scopus 로고    scopus 로고
    • Native Mode Functional Test Generation for Microprocessors with Applications to Self-Test and Design Validation
    • J.Shen, J.Abraham, "Native Mode Functional Test Generation for Microprocessors with Applications to Self-Test and Design Validation", in Proc. of the International Test Conference 1998, pp. 990-999.
    • (1998) Proc. of the International Test Conference , pp. 990-999
    • Shen, J.1    Abraham, J.2
  • 7
    • 0030245490 scopus 로고    scopus 로고
    • Hierachical Test Generation Under Architectural Level Functional Constraints
    • Sept.
    • J. Lee, J.H. Patel, "Hierachical Test Generation Under Architectural Level Functional Constraints", in IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no. 9, Sept. 1996, pp. 1144-1151
    • (1996) IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems , vol.15 , Issue.9 , pp. 1144-1151
    • Lee, J.1    Patel, J.H.2
  • 12
    • 0035248749 scopus 로고    scopus 로고
    • Realization-Independent ATPG for Designs with Unimplemented Blocks'
    • February
    • H. Kim, J. Hayes, "Realization-Independent ATPG for Designs with Unimplemented Blocks'", IEEE Transactions on CAD of Integrated Circuits and Systems, vo.20, no.2, pp. 290-306, February 2001.
    • (2001) IEEE Transactions on CAD of Integrated Circuits and Systems , vol.20 , Issue.2 , pp. 290-306
    • Kim, H.1    Hayes, J.2
  • 14
    • 0033350972 scopus 로고    scopus 로고
    • An Effective Built-In Self-Test Scheme for Parallel Multipliers
    • Sept. 99
    • D. Gizopoulos, A. Paschalis, Y. Zorian, "An Effective Built-In Self-Test Scheme for Parallel Multipliers", in IEEE Transactions on Computers, vol. 48, no.9, pp. 936-950, Sept. 99
    • IEEE Transactions on Computers , vol.48 , Issue.9 , pp. 936-950
    • Gizopoulos, D.1    Paschalis, A.2    Zorian, Y.3
  • 15
    • 11844261646 scopus 로고    scopus 로고
    • Plasma CPU Model, http://www.opencores.org/projects/mips
    • Plasma CPU Model


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.