A strategy for mixed-signal yield improvement

IEEE Design and Test of Computers

Volumn 19, Issue 3, 2002, Pages 14-23

  Bordelon, Jim ^a,b   Tranchina, Ben ^a   Madangarli, Vipin ^a   Craig, Mark ^a  

^a HPL Technologies   (United States)

^b TestChip Technologies Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG CIRCUITS; DIAGNOSTIC CIRCUITS; MIXED SIGNAL CIRCUITS; SYSTEM ON A CHIP;

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRONICS PACKAGING; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; LINEAR NETWORKS; LITHOGRAPHY; LOGIC CIRCUITS; PRINTED CIRCUIT BOARDS; SILICON WAFERS; STATIC RANDOM ACCESS STORAGE; VARIABLE FREQUENCY OSCILLATORS;

MIXER CIRCUITS;

EID: 0036575890     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (4)

1. Design for testability
2. Monte Carlo modeling of threshold variation due to dopant fluctuations
3. Resistor matching characterization for process development using D/A converter