-
1
-
-
0032314038
-
Scan chain design for test time reduction in core-based IC's
-
Oct.
-
J. Aerts and E. J. Marinissen, "Scan chain design for test time reduction in core-based IC's," in Proc. IEEE Int. Test Conf. (ITC), Oct. 1998, pp. 448-457.
-
(1998)
Proc. IEEE Int. Test Conf. (ITC)
, pp. 448-457
-
-
Aerts, J.1
Marinissen, E.J.2
-
2
-
-
85020530438
-
Scheduling malleable tasks on parallel processors to minimize the makespan
-
Bonn, Germany, May
-
J. Blazewicz, M. Y. Kovalyov, M. Machowiak, D. Trystram, and J. Weglarz, "Scheduling malleable tasks on parallel processors to minimize the makespan," in Proc. XIV European Chapter Combinatorial Optimization (ECCO), Bonn, Germany, May 2001.
-
(2001)
Proc. XIV European Chapter Combinatorial Optimization (ECCO)
-
-
Blazewicz, J.1
Kovalyov, M.Y.2
Machowiak, M.3
Trystram, D.4
Weglarz, J.5
-
3
-
-
0033683901
-
Design of system-on-a-chip test access architectures under place-and-route and power constraints
-
June
-
K. Chakrabarty, "Design of system-on-a-chip test access architectures under place-and-route and power constraints," in Proc. ACM/IEEE Design Automation Conf. (DAC), June 2000, pp. 432-437.
-
(2000)
Proc. ACM/IEEE Design Automation Conf. (DAC)
, pp. 432-437
-
-
Chakrabarty, K.1
-
4
-
-
0034292688
-
Test scheduling for core-based systems using mixed-integer linear programming
-
Oct.
-
_, "Test scheduling for core-based systems using mixed-integer linear programming," IEEE Trans. Computer-Aided Design, vol. 19, pp. 1163-1174, Oct. 2000.
-
(2000)
IEEE Trans. Computer-aided Design
, vol.19
, pp. 1163-1174
-
-
-
5
-
-
0012157888
-
Optimal test access architectures for system-on-a-chip
-
Jan.
-
_, "Optimal test access architectures for system-on-a-chip," ACM Trans, Design Automation Electron. Syst., vol. 6, pp. 26-49, Jan. 2001.
-
(2001)
ACM Trans, Design Automation Electron. Syst.
, vol.6
, pp. 26-49
-
-
-
6
-
-
0033329245
-
Low overhead design for testability and test generation technique for core-based systems-on-a-chip
-
Nov.
-
I. Ghosh, N. K. Jha, and S. Dey, "Low overhead design for testability and test generation technique for core-based systems-on-a-chip," IEEE Trans. Computer-Aided Design, vol. 18, pp. 1661-1661, Nov. 1999.
-
(1999)
IEEE Trans. Computer-aided Design
, vol.18
, pp. 1661
-
-
Ghosh, I.1
Jha, N.K.2
Dey, S.3
-
7
-
-
0142172978
-
TAM architectures and their implication on test application time
-
Marina del Ray, CA, May
-
S. K. Goel and E. J. Marinissen, "TAM architectures and their implication on test application time," in Proc. Dig. Papers IEEE Int. Workshop Testing Embedded Core-Based Systems (TECS), Marina del Ray, CA, May 2001, pp. 3.3-1-10.
-
(2001)
Proc. Dig. Papers IEEE Int. Workshop Testing Embedded Core-based Systems (TECS)
, pp. 331-3310
-
-
Goel, S.K.1
Marinissen, E.J.2
-
9
-
-
0035680777
-
Test wrapper and test access mechanism co-optimization for system-on-a-chip
-
Oct.
-
V. Iyengar, K. Chakrabarty, and E. J. Marinissen, "Test wrapper and test access mechanism co-optimization for system-on-a-chip," in Proc.IEEE Int. Test Conf. (ITC), Oct. 2001, pp. 1023-1032.
-
(2001)
Proc.IEEE Int. Test Conf. (ITC)
, pp. 1023-1032
-
-
Iyengar, V.1
Chakrabarty, K.2
Marinissen, E.J.3
-
10
-
-
84893718115
-
Efficient wrapper/TAM co-optimization for large SoCs
-
Mar.
-
_, "Efficient wrapper/TAM co-optimization for large SoCs," in Proc. Design, Automation, and Test in Europe (DATE), Mar. 2002, pp. 491-498.
-
(2002)
Proc. Design, Automation, and Test in Europe (DATE)
, pp. 491-498
-
-
-
11
-
-
13244280761
-
On using rectangle packing for SOC wrapper/TAM co-optimization
-
_, "On using rectangle packing for SOC wrapper/TAM co-optimization," in Proc. IEEE VLSI Test Symp. (VTS), 2002, pp. 253-258.
-
(2002)
Proc. IEEE VLSI Test Symp. (VTS)
, pp. 253-258
-
-
-
12
-
-
0035680667
-
CTL, the language for describing core-based test
-
Oct.
-
R. Kapur, M. Lousberg, T. Taylor, B. Keller, P. Reuter, and D. Kay, "CTL, the language for describing core-based test," in Proc. IEEE Int. Test Conf. (ITC), Oct. 2001, pp. 131-139.
-
(2001)
Proc. IEEE Int. Test Conf. (ITC)
, pp. 131-139
-
-
Kapur, R.1
Lousberg, M.2
Taylor, T.3
Keller, B.4
Reuter, P.5
Kay, D.6
-
14
-
-
0036908644
-
Formulating SoC test scheduling as a network transportation problem
-
Dec.
-
S. Koranne, "Formulating SoC test scheduling as a network transportation problem," IEEE Trans. Computer-Aided Design, vol. 21, pp. 1517-1525, Dec. 2002.
-
(2002)
IEEE Trans. Computer-aided Design
, vol.21
, pp. 1517-1525
-
-
Koranne, S.1
-
15
-
-
0034481921
-
Wrapper design for embedded core test
-
Oct.
-
E. J. Marinissen, S. K. Goel, and M. Lousberg, "Wrapper design for embedded core test," in Proc. IEEE Int. Test Conf. (ITC), Oct. 2000, pp. 911-920.
-
(2000)
Proc. IEEE Int. Test Conf. (ITC)
, pp. 911-920
-
-
Marinissen, E.J.1
Goel, S.K.2
Lousberg, M.3
-
16
-
-
85020530272
-
-
SOC Benchmark Website. [Online]
-
E. J. Marinissen, V. Iyengar, and K. Chakrabarty. (2002) ITC '02 SOC Benchmark Website. [Online]. Available: http://www.extra.research.philips.com/itc02socbenchm/
-
(2002)
ITC '02
-
-
Marinissen, E.J.1
Iyengar, V.2
Chakrabarty, K.3
-
17
-
-
0034480246
-
On using IEEE P1500 SECT sect for test plug-n-play
-
Oct.
-
E. J. Marinissen, R. Kapur, and Y. Zorian, "On using IEEE P1500 SECT sect for test plug-n-play," in Proc. IEEE Int. Test Conf. (ITC), Oct. 2000, pp. 770-777.
-
(2000)
Proc. IEEE Int. Test Conf. (ITC)
, pp. 770-777
-
-
Marinissen, E.J.1
Kapur, R.2
Zorian, Y.3
-
18
-
-
0032308284
-
A structured test re-use methodology for core-based system chips
-
Oct.
-
P. Varma and S. Bhatia, "A structured test re-use methodology for core-based system chips," in Proc. IEEE Int. Test Conf. (ITC), Oct. 1998, pp. 294-302.
-
(1998)
Proc. IEEE Int. Test Conf. (ITC)
, pp. 294-302
-
-
Varma, P.1
Bhatia, S.2
-
19
-
-
0031367231
-
Test requirements for embedded core-based systems and IEEE P1500
-
Nov.
-
Y. Zorian, "Test requirements for embedded core-based systems and IEEE P1500," in Proc. IEEE Int. Test Conf. (ITC), Nov. 1997, pp. 191-199.
-
(1997)
Proc. IEEE Int. Test Conf. (ITC)
, pp. 191-199
-
-
Zorian, Y.1
-
20
-
-
0032306079
-
Testing embedded-core based system chips
-
Oct.
-
Y. Zorian, E. J. Marinissen, and S. Dey, "Testing embedded-core based system chips," in Proc. IEEE Int. Test Conf. (ITC), Oct. 1998, pp. 130-143.
-
(1998)
Proc. IEEE Int. Test Conf. (ITC)
, pp. 130-143
-
-
Zorian, Y.1
Marinissen, E.J.2
Dey, S.3
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