Robustness IPs for reliability and security of SoCs

IEEE International Test Conference (TC)

Volumn , Issue , 2002, Pages 357-360

  Dupont, Eric ^a   Nicolaidis, Michael ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONICS INDUSTRY; INTEGRATED CIRCUIT LAYOUT; MARKETING; MICROPROCESSOR CHIPS; RADIATION EFFECTS; RELIABILITY; SECURITY OF DATA; SEMICONDUCTING SILICON; VLSI CIRCUITS;

REGISTER TRANSFER LEVEL; SIGNAL INTEGRITY; VERY DEEP SUBMICRON;

INTEGRATED CIRCUIT TESTING;

EID: 0036446821     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. L. Anghel and M. Nicolaidis, "Cost Reduction and Evaluation of a Temporary Faults Detecting Technique," Proc. 2000 Design Automation and Test in Europe Conf. (DATE 00), ACM Press, New York, 2000, pp. 591-598.
2. N.A. Touba and E.J. McCluskey "Logic Synthesis of Multilevel Circuits with Concurrent Error Detection," IEEE Trans. CAD, vol. 16, no. 7, July 1997, pp. 783-789.
3. Y.Zorian, "Embedding Infrastructure IPs for SoC yield improvement", Proc.2002 Design Automation Conference in New Orleans (DAC02)