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Volumn , Issue , 2002, Pages 357-360

Robustness IPs for reliability and security of SoCs

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONICS INDUSTRY; INTEGRATED CIRCUIT LAYOUT; MARKETING; MICROPROCESSOR CHIPS; RADIATION EFFECTS; RELIABILITY; SECURITY OF DATA; SEMICONDUCTING SILICON; VLSI CIRCUITS;

EID: 0036446821     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (3)

References (3)
  • 2
    • 0031177081 scopus 로고    scopus 로고
    • Logic synthesis of multilevel circuits with concurrent error detection
    • July
    • N.A. Touba and E.J. McCluskey "Logic Synthesis of Multilevel Circuits with Concurrent Error Detection," IEEE Trans. CAD, vol. 16, no. 7, July 1997, pp. 783-789.
    • (1997) IEEE Trans. CAD , vol.16 , Issue.7 , pp. 783-789
    • Touba, N.A.1    McCluskey, E.J.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.