Hybrid soft error detection by means of infrastructure IP cores

Proceedings - 10th IEEE International On-Line Testing Symposium, IOLTS 2004

Volumn , Issue , 2004, Pages 79-84

  Bolzani, L ^a   Rebaudengo, M ^b   Sonza Reorda, M ^b   Vargas, F ^a   Violante, M ^b  

^a PONTIFICAL CATHOLIC UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

^b POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

FAULT DETECTION; GROUND LEVEL; OPERATIONS REDUNDANCIES; TRANSIENT BIT FLIP FAULT;

ALGORITHMS; COMPUTER AIDED MANUFACTURING; COMPUTER SOFTWARE; COMPUTER SYSTEMS; FLIP FLOP CIRCUITS; INTELLECTUAL PROPERTY; MATHEMATICAL MODELS; PERTURBATION TECHNIQUES; SENSITIVITY ANALYSIS;

ERROR DETECTION;

EID: 10444251014     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/OLT.2004.1319663     Document Type: Conference Paper

References (11)

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