Embedded-memory test and repair: Infrastructure IP for SoC yield

IEEE Design and Test of Computers

Volumn 20, Issue 3, 2003, Pages 58-66

  Zorian, Yervant ^a   Shoukourian, Samvel ^a  

^a Virage Logic   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPARATOR CIRCUITS; COSTS; LEAKAGE CURRENTS; PROBLEM SOLVING; SILICON;

MEMORY-DOMINANT CHIPS;

MICROPROCESSOR CHIPS;

EID: 0037706756     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2003.1198687     Document Type: Article

References (12)

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2. I. Kim et al., "Built-in Self-Repair for Embedded High Density SRAM," Proc. Int'l Test Conf. (ITC 98), IEEE Press, 1998, pp. 1112-1119.
3. Y. Zorian, "Embedded Memory Test & Repair: Infrastructure IP for SOC Yield," Proc. Int'l Test Conf. (ITC 02), IEEE Press, 2002, pp. 340-349.
4. J. Segal et al., "Determining Redundancy Requirements for Memory Arrays with Critical Area Analysis," Proc. IEEE Memory Technology, Design and Testing Workshop (MTDT 99), IEEE CS Press, 1999, pp. 48-53.
5. Y. Zorian, "What Is Infrastructure IP?" IEEE Design & Test, vol. 19, no 3, May-June 2002, pp. 5-7.
6. Y. Zorian, "Embedded Infrastructure IP for SOC Yield Improvement," Proc, 39th Design Automation Conf. (DAC 02), ACM Press, 2002, pp. 709-712.
7. Y. Zorian, E.J. Marinissen, and S. Dey, "Testing Embedded Core-Based System Chips," Proc. Int'l Test Conf. (ITC 98), IEEE Press, 1998, pp. 130-143.
8. E. Rondey, Y. Telller, and S. Borri, "A Silicon-Based Yield Gain Evaluation Methodology for Embedded SRAMs with Different Redundancy Scenarios," Proc. IEEE Memory Technology, Design and Testing Workshop (MTDT 02), IEEE CS Press, 2002, pp. 57-61.
9. J. Kawagoe et al., "A Built-in Self-Repair Analyzer (CRESTA) for Embedded DRAM," Proc. Int'l Test Conf. (ITC 00), IEEE CS Press, 2000, pp. 567-574.
10. S. Shoukourian, V. Vardanian, and Y. Zorian, "An Approach for Evaluation of Redundancy Analysis Algorithms," Proc. IEEE Memory Technology, Design and Testing Workshop (MTDT 01), IEEE CS Press, 2001, pp. 51-55.
11. A.J. van de Goor and I. Schanstra, "Address and Data Scrambling: Causes and Impact on Memory Tests," Proc. 1st IEEE Int'l Workshop on Electronic Design, Test and Applications (DELTA 02), IEEE Press, 2002, pp. 128-136.
12. D.K. Bhavsar, "An Algorithm for Row-Column SelfRepair of RAMs and Its Implementation in the Alpha 21264," Proc. Int'l Test Conf. (ITC 99), IEEE Press, 1999, pp. 311-318.