Clustered loop buffer organization for low energy VLIW embedded processors

IEEE Transactions on Computers

Volumn 54, Issue 6, 2005, Pages 672-683

  Jayapala, Murali ^a   Barat, Francisco ^a   Aa, Tom Vander ^a   Catthoor, Francky ^b   Corporaal, Henk ^c   Deconinck, Geert ^a  

^a UNIVERSITY OF LEUVEN   (Belgium)

^b IMEC   (Belgium)

^c EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

Low power design; Memory design; Memory management; Real time and embedded systems; RISC CISC; VLIW architectures

Indexed keywords

CACHE MEMORY; COMPUTER SIMULATION; DATA STORAGE EQUIPMENT; EMBEDDED SYSTEMS; OPTIMIZATION; REAL TIME SYSTEMS; VERY LONG INSTRUCTION WORD ARCHITECTURE;

EMBEDDED PROCESSORS; LOW POWER DESIGN; MEMORY DESIGN; MEMORY MANAGEMENT;

MICROPROCESSOR CHIPS;

EID: 21044438482     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2005.92     Document Type: Article

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