A power reduction technique with object code merging for application specific embedded processors

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2000, Pages 617-623

  Ishihara, Tohru ^a   Yasuura, Hiroto ^a  

^a KYUSHU UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC; BENCHMARK PROGRAMS; EMBEDDED PROCESSORS; ENERGY REDUCTION; INSTRUCTION MEMORY; OBJECT CODE; POWER REDUCTION TECHNIQUES; READ-ONLY MEMORY;

EXHIBITIONS;

MERGING;

EID: 21044436759     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2000.840849     Document Type: Conference Paper

References (10)

1. Nikolaos Bellas, and Ibrahim Hajj,. "Architectural and Compiler Support for Energy Reduction in the Memory Hierarchy of High Performance Microprocessors". In Proc. of International Symposium on Low Power Electronics and Design, pages 70-75, 1998.
2. C.-L. Su and A. M. Despain. "Cache Design Tradeo s for Power and Performance Optimization: A Case Study". In Int'l Symp. on Low Power Design( ISLPD'95), pages 282-286, 1995.
3. Y. Yoshida, B. Y. Song, H. Okuhata, T. Onoye, and I. Shirakawa . "An Object Code Compression Approach to Embedded Processors". In Proc. of Int'l Symposium on Low Power Electronics and Design, pages 265-268, Aug. 1997.
4. K. Ogawa. "PASTEL: A Parametrized Memory Characterization System". In Proc. of Design, Automation and Test in Europe, March 1998.
5. H. Shinohara T. Yoshihara H. Takagi S. Nagao S. Kayano M. Yoshimoto, K. Anami and T. Nakano. "A Divided Word-Line Structure in the Staticture in the Static RAM and its Application to a 64K Full CMOS RAM". IEEE Journal of Solid-State Circuits, pages 479-485, June 1983.
6. M. Isobe, J. Matsunaga, T. Sakurai, T. Ohtani, K. Sawada, H. Nozawa, T. Iszuka and S. Kohyama. "A Low Power 46ns 256K bit CMOS Static RAM with Dynamic Double Word Line". IEEE Journal of Solid State Circuits, SC-19(5):578-585, May 1984.
7. Edwin de Angel and Jr. Earl E. Swartslander. \Survey of Low Power Techniques for ROMs". In Proc. of Int'l Symposium on Low Power Electronics and Design, pages 7-11, 1997.
8. T. Sakurai, and T. Iizuka. "DoubleWord Line and Bit Line Structure for VLSI RAMs -Reduction of Word Line and Bit Line Delay". In Extended Abstracts of the 15th Conf. on Solid State Devices and Materials, pages 269-272, 1983.
9. L. Benini, A. Macii, E. Macii, and M. Pancino. "Selective Instruction Compression for Memory Energy Reduction in Embedded System". In Proc. of Int'l Symposium on Low Power Electronics and Design, pages 206-211, Aug. 1999.
10. J. L. Hennessy and D. A. Patterson. "Computer Architecture: A Quantitative Approach". Morgan Kaufmann Publishers, Inc., 2nd edition, 1996.