Compressed Code Execution on DSP Architectures

Proceedings of the International Symposium on System Synthesis

Volumn Part F129194, Issue , 1999, Pages

  Centoducatte, Paulo ^a   Araujo, Guido ^a   Pannain, Ricardo ^b  

^a UNIVERSITY OF CAMPINAS   (Brazil)

^b PONTIFÍCIA UNIVERSIDADE CATÓLICA DE CAMPINAS   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL SIGNAL PROCESSING; EMBEDDED SYSTEMS; ENGINES; INTEGRATED CIRCUIT DESIGN;

COMPRESSED CODES; DECOMPRESSION ENGINES; DSP ARCHITECTURES; GATE LEVEL SIMULATION; MASS PRODUCTION; OPERATION FREQUENCY; PROGRAM EXECUTION; RISC ARCHITECTURE;

CODES (SYMBOLS);

EID: 21044440254     PISSN: 10801820     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/isss.1999.814261     Document Type: Conference Paper

References (12)

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