Filtering memory references to increase energy efficiency

IEEE Transactions on Computers

Volumn 49, Issue 1, 2000, Pages 1-15

  Kin, Johnson ^a,b   Gupta, Munish ^c   Mangione Smith, William H ^a,b  

^a IEEE   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c International Rectifier Corp Italy   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED PROCESSOR; FILTER CACHE; FILTERING MEMORY REFERENCES; MEDIA PROCESSOR;

DATA HANDLING; EMBEDDED SYSTEMS; ENERGY EFFICIENCY; MICROPROCESSOR CHIPS; PERFORMANCE; RANDOM ACCESS STORAGE;

BUFFER STORAGE;

EID: 0033889397     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.822560     Document Type: Article

References (23)

1. D.A. Patterson and J.L. Hennessy, Large and Fast: Exploiting Memory Hierarchy, Computer Organization & Design The Hardware/ Software Interface. Morgan Kaufmann, 1994.
2. J. Montanaro et al., "A 160MHz 32b 0.5W CMOS RISC Microprocessor," Proc. Int'l Solid-State Circuits Conf., 1996.
3. R. Bechade et al., "A 32b 66MHz 1.8W Microprocessor," Proc. Int'l Solid-State Circuits Conf., 1994.
4. E. Harris et al., "Technology Directions for Portable Computers," Proc. IEEE, vol. 83, no. 4, Apr. 1995.
5. R.P. Colwell and R.L. Steck, "A 0.6μm BiCMOS Processor with Dynamic Execution," Proc. IEEE Int'l Solid-State Circuits Conf., 1995.
6. R. Gonzalez and M. Horowitz, "Energy Dissipation in General Purpose Microprocessors," IEEE J. Solid State Circuits, vol. 31, no. 9, pp. 1,277-1,284, 1996.
7. N.H.E. Weste and K. Eshraghian, "Circuit Characterization and Performance Estimation," Principles of CMOS VLSI Design, Addison Wesley, 1994.
8. R. Sykes, "Texas Instruments Announces Chip Technology Breakthrough," IDG News Service, 1997.
9. B. Davari, R. Dennard, and G. Shahidi, "CMOS Scaling for High Performance and Low Power - The Next Ten Years," Proc. IEEE, vol. 83, no. 4, Apr. 1995.
10. K. Itoh, K. Sasaki, and Y. Nakagome, "Trends in Low-Power RAM Circuit Technologies," Proc. IEEE, vol. 83, no. 4, Apr. 1995.
11. J. Frenkil, "A Multi-Level Approach to Low-Power IC Design," IEEE Spectrum, vol. 35, no. 2, 1998.
12. M.J. Flynn, Computer Architecture: Pipelined and Parallel Processor Design. Jones and Bartlett, 1996.
13. M.B. Kamble and K. Ghose, "Energy-Efficiency of VLSI Caches: A Comparative Study," Proc. Int'l Conf. VLSI Design, 1997.
14. M.B. Kamble and K. Ghose, "Analytical Energy Dissipation Models for Low Power Caches," Proc. Int'l Symp. Low-Power Electronics and Design, 1997.
15. S.E. Wilton and N. Jouppi, "An Enhanced Access and Cycle Time Model for On-Chip Caches," DEC WRL, report 93/5, 1994.
16. C. Su and A. Despain, "Cache Design Tradeoffs for Power and Performance Optimization: A Case Study," Proc. Int'l Symp. Low Power Design, 1995.
17. U. Ko, P.T. Balsara, and A.K. Nanda, "Energy Optimization of Multi-Level Processor Cache Architectures," Proc. Int'l Symp. Low Power Design, 1995.
18. J. Turley, "ARM Grabs Embedded Speed Lead," Microprocessor Report, 1996.
19. P.P. Chang et al., "IMPACT: An Architectural Framework for Multiple-Instruction-Issue Processors," Proc. Int'l Symp. Computer Architecture, 1991.
20. C. Lee, M. Potkonjak, and W.H. Mangione-Smith, "MediaBench: A Tool for Evaluating Multimedia and Communications Systems," Proc. Micro 30, 1997.
21. B. Schneier, Applied Cryptography: Protocols, Algorithms, and Source Code in C. New York: John Wiley & Sons, 1996.
22. A. Watt, 3D Computer Graphics, second ed. Addison-Wesley, 1993.
23. U. Ko, P.T. Balsara, and A.K. Nanda, "Energy Optimization of Multilevel Cache Architectures for RISC and CISC Processors," IEEE Trans. Very Large Scale Integration Systems, vol. 6, no. 2, June 1998.