Throughput-driven floorplanning with wire pipelining

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 24, Issue 5, 2005, Pages 663-675

  Casu, Mario R ^a   Macchiarulo, Luca ^b  

^a POLITECNICO DI TORINO   (Italy)

^b University of Hawaii at Manoa   (United States)

Author keywords

Floorplanning; Systems on chip (SoC); Throughput; Wire pipelining

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; FLIP FLOP CIRCUITS; FORMAL LOGIC; MICROPROCESSOR CHIPS; SEMICONDUCTOR DEVICE MANUFACTURE; SIMULATED ANNEALING; THROUGHPUT;

FLOORPLANNING; SYSTEMS-ON-CHIP (SOC); TECHNOLOGY SCALING; WIRE PIPELINING;

INTEGRATED CIRCUIT LAYOUT;

EID: 18744403117     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.846371     Document Type: Article

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