An integrated floorplanning with an efficient buffer planning algorithm

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2003, Pages 136-142

  Ma, Yuchun ^a   Hong, Xianlong ^a   Dong, Sheqin ^a   Chen, Song ^a   Cai, Yici ^a   Cheng, C K ^b   Gu, Jun ^c  

^a TSINGHUA UNIVERSITY   (China)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c UNIVERSITY OF HONG KONG   (Hong Kong)

Author keywords

Buffer Insertion; Floorplaning; Routability

Indexed keywords

ALGORITHMS; BUFFER STORAGE; COMPUTATIONAL COMPLEXITY; MICROPROCESSOR CHIPS;

FLOORPLANNING;

INTEGRATED CIRCUITS;

EID: 0038378488     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/640000.640031     Document Type: Conference Paper

References (11)

1. J. Cong, T.Kong, and D. Z. Pan, "Buffer block planning for interconnectdriven floorplanning," in Proc. Int. Conf. Computer-Aided Design, Nov. 1999, pp. 358-363.
2. C. J. Alpert and A. Devgan, "Wire segmenting for improved buffer insertion,"in Proc. Design Automation Conf., June 1997, pp. 588-593.
3. P. Sarkar, V. Sundararaman, and C. K. Koh. Routability-driven repeater block planning for interconnectcentric.floorplanning. In ISPD 2000.
4. Hong Xianlong, Huang Gang et al. "Corner Block List: An Effective and Efficient Topological Representation of Nonslicing Floorplan" ICCAD'2000.pp.8-12.
5. J. Cong, L. He, K.-Y. Khoo, C.-K, Koh, and Z. Pan, "Interconnect design for deep submicron ICs," in Proc. Int. Conf. Computer-Aided Design, Nov. 1997, pp. 478-485.
6. W. C. Elmore, "The transient response of damped linear networks with particular regard to wide-band amplifiers," J. Appl. Phys., vol. 19, pp.55-63, Jan. 1948.
7. J. Cong and D. Z. Pan, "Interconnect delay estimation models for synthesis and design planning," in Proc. ASP Design Automation Conf., Jan. 1999, pp. 97-100.
8. J. Cong. " Challenges and opportunities for design innovations in nanometer technologies". In Frontiers in Semiconductor Research: A Collection of SRC Working Papers, 1997.
9. X. P. Tang and D. Wong. "Planning buffer locations by network flows". In Intl. Symp. Physical Design, pages 186-191, 2000.
10. Semiconductor Industry Association, National Technology Roadmap for Semiconductors. San Jose, CA: SIA, 1997.
11. C. J. Alpert, J. Hu, S. S. Sapatnekar, and P. G.Villarrubia. "A practical methodology for early buffer and wire resource allocation". In DAC, 2001.