Optimal design of synchronous circuits using software pipelining techniques

ACM Transactions on Design Automation of Electronic Systems

Volumn 6, Issue 4, 2001, Pages 516-532

  Boyer, François R ^a   Aboulhamid, El Mostapha ^a   Savaria, Yvon ^b   Boyer, Michel ^a  

^a UNIVERSITÉ DE MONTRÉAL   (Canada)

^b ÉCOLE POLYTECHNIQUE DE MONTRÉAL   (Canada)

Author keywords

Algorithms; Performance; Resynthesis; Retiming; Software pipelining

Indexed keywords

EID: 23044531573     PISSN: 10844309     EISSN: None     Source Type: Journal    
DOI: 10.1145/502175.502180     Document Type: Article

References (17)

1. BENCHMARKS. 1996. Dept. of Computer Science, Collab. Benchmark Lab., North Carolina State University, http://www.cbl.ncsu.edu/benchmarks/Benchmarks-upto-1996.html.
2. BENNOUR, I. E., AND ABOULHAMID, E. M. 1995. Les problèmes d'ordonnancement cycliques dans la synthèse de systèmes numériques. Tech. Rep. 996 (Oct.). DIRO, Université de Montréal, Montréal Que., Canada, http://www.iro.umontreal.ca/~aboulham/pipeline.pdf.
3. DE MICHELI, G. 1994. Synthesis and optimization of digital circuits. McGraw-Hill, New York.
4. DEOKAR, R. B., AND SAPATNEKAR, S. 1995. A fresh look at retiming via clock skew optimization. In Proceedings of DAC'95. ACM, New York, pp. 310-315.
5. FRASER, C. W., AND HANSON, D. R. 1995. A Retargetable C Compiler: Design and Implementation. Benjamin Cummings.
6. HANEN, C. 1994. Study of a NP-hard cyclic scheduling problem: The recurrent job-shop. Europ. J. Oper. Res. 72, 1, 82-101.
7. HARTMANN, M., AND ORLIN, J. 1993. Finding minimum cost to time ratio cycles with small integral transit times. Networks; an international journal 23, 6, 567-574.
8. HWANG, C.-T., Hsu, Y.-C., AND LIN, Y.-L. 1991. Scheduling for functional pipelining and loop winding. In Proceedings of DAC'91. ACM, New York, pp. 764-769.
9. ISHII, A. T., LEISERSON, C. E., AND PAPAEFTHYMIOU, M. C. 1997. Optimizing two-phase, level-clocked circuitry. J. ACM 44, 1 (Jan.), 148-199.
10. LAWLER, E. 1976. Combinatorial Optimization: Networks and Matroids. Saunders College Publishing, Fort Worth, Tex.
11. LEGL, C., VANBEKBERGEN, P., AND WANG, A. 1997. Retiming of edge-triggered circuits with multiple clocks and load enables. In Proceedings of IWLS'97.
12. LEISERSON, C. E., AND SAXE, J. B. 1991. Retiming synchronous circuitry. Algorithmica 6, 1, 5-35.
13. LOCKYEAR, B., AND EBELING, C. 1994. Optimal retiming of level-clocked circuits using symmetric clock schedules. IEEE Trans. Comput. Aided Desi. Integ. Circ. Syst. 13, 9 (Sept.), 1097-1109.
14. MAHESHWARI, N., AND SAPATNEKAR, S. 1997. An improved algorithm for minimum-area retiming. In Proceedings of DAC'97. ACM, New York, pp. 2-7.
15. MAHESHWARI, N., AND SAPATNEKAR, S. 1998. Efficient retiming of large circuits. IEEE Trans. VLSI Syst. 6, 1 (March), 74-83.
16. SAKALLAH, K. A., MUDGE, T. N., AND OLUKTUN, O. A. 1991. Analysis and design of latch-controlled synchronous digital circuits. In Proceedings of DAC'90. ACM, New York, pp. 111-117.
17. VAN DONGEN, V. H., GAO, G. R., AND NING, Q. 1992. A polynomial time method for optimal software pipelining. In Proceedings of CONPAR'92. Lecture Notes in Computer Sciences, No. 634. Springer-Verlag, New York, pp. 613-624.