Retiming with Interconnect and Gate Delay

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2003, Pages 221-226

  Chu, Chris ^a   Young, Evangeline F Y ^b   Tong, Dennis K Y ^b   Dechu, Sampath ^c  

^a Iowa State University   (United States)

^b CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

^c MICRON TECHNOLOGY INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CONSTRAINT THEORY; GATES (TRANSISTOR); HEURISTIC METHODS; INTERCONNECTION NETWORKS; LINEAR PROGRAMMING; LOGIC CIRCUITS; MATHEMATICAL MODELS; POLYNOMIALS; PROBLEM SOLVING;

CIRCUIT PARTITIONING; GATE DELAY;

SEQUENTIAL CIRCUITS;

EID: 0346778795     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iccad.2003.159693     Document Type: Conference Paper

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