A new approach to Latency Insensitive Design

Proceedings - Design Automation Conference

Volumn , Issue , 2004, Pages 576-581

  Casu, Mario R ^a   Macchiarulo, Luca ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

Interconnections; Pipelining; System on Chip

Indexed keywords

ALGORITHMS; CLOCKS; COMMUNICATION CHANNELS (INFORMATION THEORY); COMMUNICATION SYSTEMS; COMPUTATIONAL COMPLEXITY; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; SCHEDULING;

LATENCY INSENSITIVE PROTOCOLS (LIP); PIPELINING; SYSTEM ON CHIPS;

INTEGRATED CIRCUIT LAYOUT;

EID: 4444341106     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/996566.996725     Document Type: Conference Paper

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