A Methodology for Optimal Repeater Insertion in Pipelined Interconnects

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 22, Issue 12, 2003, Pages 1613-1624

  Cocchini, Pasquale ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Dynamic programming; Integrated circuit interconnections; Pipelines; Repeaters

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTATIONAL COMPLEXITY; DYNAMIC PROGRAMMING; ELECTRIC CLOCKS; ELECTRIC CONNECTORS; ELECTRIC NETWORK TOPOLOGY; FLIP FLOP CIRCUITS; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; PIPELINE PROCESSING SYSTEMS; SIGNAL RECEIVERS; TREES (MATHEMATICS); VLSI CIRCUITS;

INTEGRATED CIRCUIT INTERCONNECTS; NETWORK LATENCY;

TELECOMMUNICATION REPEATERS;

EID: 0346055230     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2003.819422     Document Type: Article

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