Floorplanning of pipelined array modules using sequence pairs

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2003, Pages 143-150

  Moe, Matthew ^a   Schmit, Herman ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

Floorplan; Pipelined Array; Sequence Pair

Indexed keywords

ARRAYS; DIGITAL SIGNAL PROCESSING; GRAPH THEORY; MICROPROCESSOR CHIPS;

PIPELINED ARRAYS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0038040200     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/640000.640032     Document Type: Conference Paper

References (13)

1. J. Crenshaw, M. Sarrafzadeh, P. Banerjee, P. Prabhakaran, "An incremental floorplanner," in Proc. Ninth Great Lakes Symposium on VLSI, pp. 248-251, 1999.
2. Y.M. Fang, D.F. Wong, "Simultaneous Functional-Unit Binding and Floorplanning", in Proc. ICCAD, pps. 317-321, 1994.
3. H. Murata, K. Fujiyoshi, S. Nakatake, Y. Kajitani, "VLSI Module Placement Based on Rectangle Packing by the Sequence Pair," IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, vol. 15, no. 12, pp. 1518-1524, December 1996.
4. L. Stockmeyer, "Optimal orientations of cells in slicing floorplan designs," Inform. Contr., vol. 57, pp. 91-101, 1983.
5. S. Wimer, I. Koren, I. Cederbai,. "Optimal Aspect Ratios of Building Blocks in VLSI," IEEE Trans. on Computer Aided Design, vol. 8, no. 2, pp. 139-145, December 1996.
6. H. Murata and E. S. Kuh, "Sequence-pair based placement method for hard/soft/preplaced modules," in Proc. Int. Symp. Physical Design, Apr. 1998. pp. 167-172.
7. P. M. Vaidya, "A New Algorithm for minimizing convex functions over convex sets," Mathematical Programming, 73:291-341, 1996.
8. F. Y. Young, C. C. N. Chu, W.S. Luk, and Y. C. Wong, "Handling Soft Modules in General Nonslicing Floorplan Using Lagrangian Relaxation," in IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, vol. 20, no. 5, pp. 687692, May 2001.
9. http://www.cse.ucsc.edu/research/surf/GSRC/progress.html#V.
10. Bruce Schneier, Applied Cryptography, Second Edition, John Wiley & Sons, Inc., 1996, pp. 319-325.
11. R. G. Gallager "Low Density Parity Check Nodes," IRE Trans. Inform. Theory, Jan. 1962, pp. 21-28.
12. "Design Compiler Reference Manual", Synopsys Inc., 1999.
13. "Dolphin 2.0 Online Help", Monterey Design Systems, December 2000.