Optimal buffered routing path constructions for single and multiple clock domain systems

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2002, Pages 247-253

  Hassoun, Soha ^a   Alpert, Charles J ^b   Thiagarajan, Meera ^a  

^a TUFTS UNIVERSITY   (United States)

^b IBM AUSTIN RESEARCH LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER INSERTION; MULTIPLE CLOCK CYCLE; ROUTING PATH;

ALGORITHMS; ESTIMATION; INTELLECTUAL PROPERTY; MICROPROCESSOR CHIPS; POLYNOMIALS; PROBLEM SOLVING; SYNCHRONIZATION;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036915663     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/774572.774609     Document Type: Conference Paper

References (13)

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