IEEE P1500-compliant test wrapper design for hierarchical cores

Proceedings - International Test Conference

Volumn , Issue , 2004, Pages 1203-1212

  Sehgal, Anuja ^a   Goel, Sandeep Kumar ^b   Marinissen, Erik Jan ^b   Chakrabarty, Krishnendu ^a  

^a Duke University   (United States)

^b PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; HEURISTIC METHODS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; MULTIPLEXING EQUIPMENT; OPTIMIZATION; SEMICONDUCTOR MATERIALS;

HIERARCHICAL CORES; SYSTEM-ON-CHIPS (SOC); TEST ACCESS MECHANISMS (TAM); WRAPPER DESIGN;

PACKAGING;

EID: 18144383915     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (22)

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