Core-clustering based SoC test scheduling optimization

Proceedings of the Asian Test Symposium

Volumn 2002-January, Issue , 2002, Pages 405-410

  Huang, Yu ^a   Reddy, S M ^b   Cheng, Wu Tung ^a  

^a MENTOR GRAPHICS CORPORATION   (United States)

^b UNIVERSITY OF IOWA   (United States)

Author keywords

Cities and towns; Clustering algorithms; Energy consumption; Graphics; Heuristic algorithms; Job shop scheduling; Pins; Processor scheduling; Tellurium; Testing

Indexed keywords

ALGORITHMS; ENERGY UTILIZATION; HEURISTIC ALGORITHMS; JOB SHOP SCHEDULING; MICROPROCESSOR CHIPS; OPTIMIZATION; SCHEDULING; SYSTEM-ON-CHIP; TELLURIUM; TELLURIUM COMPOUNDS; TESTING;

CITIES AND TOWNS; COMPLETION TIME; CORE-BASED SOCS; GRAPHICS; OPTIMAL SOLUTIONS; PINS; PROCESSOR SCHEDULING; SOC TEST SCHEDULING;

CLUSTERING ALGORITHMS;

EID: 18144406404     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ATS.2002.1181745     Document Type: Conference Paper

References (5)

1. V. Iyengar, K. Chakrabarty, and E.J. Marinissen, "Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip," pp. 1023-1032, International Test Conference 2001.
2. Y. Huang, W.-T. Cheng, C.-C. Tsai, N. Mukherjee, O. Samman, Y. Zaidan, S. M. Reddy, "Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SOC Design," pp.265-270, ATS 2001
3. Y. Huang, S.M. Reddy, W.-T. Cheng, P. Reuter, N. Mukherjee, C.-C. Tsai, O. Samman, Y. Zaidan, "Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-Dimensional Bin Packing Algorithm," International Test Conference 2002, to appear .
4. D. Bagchi, D.R.Chowdhury, and J. Mukherjee, "A Novel Strategy to Test Core Based Designs," pp.122-127, VLSI Design 2001.
5. http://www.extra.research.philips.com/itc02socbenchm/