Obtaining high defect coverage for frequency-dependent defects in complex ASICs

IEEE Design and Test of Computers

Volumn 20, Issue 5, 2003, Pages 46-53

  Madge, Robert ^a   Benware, Brady R ^a   Daasch, W Robert ^b  

^a AGERE SYSTEMS   (United States)

^b PORTLAND STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BUILT-IN SELF TEST; DELAY CIRCUITS; DESIGN FOR TESTABILITY; FREQUENCY DOMAIN ANALYSIS; INTEGRATED CIRCUIT TESTING; STATISTICAL METHODS;

AUTOMATIC TEST PATTERN GENERATOR; FREQUENCY DEPENDENT DEFECTS; TRANSITION DELAY FAULT;

COMPUTER TESTING;

EID: 0142039788     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2003.1232256     Document Type: Article

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