Efficient Scan Chain Design for Power Minimization during Scan Testing Under Routing Constraint

IEEE International Test Conference (TC)

Volumn , Issue , 2003, Pages 488-493

  Bonhomme, Y ^b   Girard, P ^b   Guiller, L ^a   Landrault, C ^b   Pravossoudovitch, S ^b  

^a SYNOPSYS INC   (United States)

^b NONE

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN FOR TESTABILITY; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION;

SCAN CELLS;

INTEGRATED CIRCUITS;

EID: 0142246916     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (20)

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