Double-Tree Scan: A Novel Low-Power Scan-Path Architecture

IEEE International Test Conference (TC)

Volumn , Issue , 2003, Pages 470-479

  Bhattacharya, Bhargab B ^a   Seth, Sharad C ^b   Zhang, Sheng ^b  

^a INDIAN STATISTICAL INSTITUTE   (India)

^b UNIVERSITY OF NEBRASKA LINCOLN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; VLSI CIRCUITS;

SCAN ARCHITECTURES;

FLIP FLOP CIRCUITS;

EID: 0142246919     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (21)

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