Achieving at-speed structural test

IEEE Design and Test of Computers

Volumn 20, Issue 5, 2003, Pages 26-33

  Pateras, Stephen ^a  

^a LogicVision Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS; COMPUTER SIMULATION; DEFECTS; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT MANUFACTURE; INTERFACES (COMPUTER); SEQUENTIAL CIRCUITS; SIGNAL PROCESSING; TIMING CIRCUITS;

AT-SPEED STRUCTURAL TEST; DEVICE UNDER TEST; PRODUCT QUALITY; SCAN-BASED TESTING;

BUILT-IN SELF TEST;

EID: 0142071674     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2003.1232253     Document Type: Article

References (8)

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