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Volumn 20, Issue 5, 2003, Pages 34-40

AC scan path selection for physical debugging

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; COMPUTER DEBUGGING; DESIGN FOR TESTABILITY; TIME SERIES ANALYSIS; VECTOR QUANTIZATION;

EID: 0142103281     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2003.1232254     Document Type: Article
Times cited : (14)

References (12)
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    • IDDQ and AC scan: The war against unmodelled defects
    • IEEE Press
    • P.C. Maxwell et al., "IDDQ and AC Scan: The War Against Unmodelled Defects," Proc. Int'l Test Conf. (ITC 96), IEEE Press, 1996, pp. 250-258.
    • (1996) Proc. Int'l Test Conf. (ITC 96) , pp. 250-258
    • Maxwell, P.C.1
  • 2
    • 0031380362 scopus 로고    scopus 로고
    • Effective path selection for delay fault testing of sequential circuits
    • IEEE Press
    • T.J. Chakraborty and V.D. Agrawal, "Effective Path Selection for Delay Fault Testing of Sequential Circuits," Proc. Int'l Test Conf. (ITC 97), IEEE Press, 1997, pp. 998-1003.
    • (1997) Proc. Int'l Test Conf. (ITC 97) , pp. 998-1003
    • Chakraborty, T.J.1    Agrawal, V.D.2
  • 3
    • 0033316674 scopus 로고    scopus 로고
    • Test generation for crosstalk-induced delay in integrated circuits
    • IEEE Press
    • W.-Y. Chen et al., "Test Generation for Crosstalk-Induced Delay in Integrated Circuits," Proc. Int'l Test Conf. (ITC 99), IEEE Press, 1999, pp. 191-200.
    • (1999) Proc. Int'l Test Conf. (ITC 99) , pp. 191-200
    • Chen, W.-Y.1
  • 4
    • 0000059130 scopus 로고
    • Fastpath: A path delay test generator for standard scan designs
    • IEEE Press
    • B. Underwood et al., "Fastpath: A Path Delay Test Generator for Standard Scan Designs," Proc. Int'l Test Conf. (ITC 94), IEEE Press, 1994, pp. 154-163.
    • (1994) Proc. Int'l Test Conf. (ITC 94) , pp. 154-163
    • Underwood, B.1
  • 6
    • 0031248029 scopus 로고    scopus 로고
    • Designing and verifying embedded microprocessors
    • Oct.-Dec
    • A. Crouch and J. Freeman, "Designing and Verifying Embedded Microprocessors," IEEE Design & Test, 14, no. 4, Oct.-Dec. 1997, pp. 87-94.
    • (1997) IEEE Design & Test , vol.14 , Issue.4 , pp. 87-94
    • Crouch, A.1    Freeman, J.2
  • 7
    • 0031358774 scopus 로고    scopus 로고
    • A case study of the test development for the 2nd generation ColdFire microprocessors
    • IEEE Press
    • D. Amason et al., "A Case Study of the Test Development for the 2nd Generation ColdFire Microprocessors," Proc. Int'l Test Conf. (ITC 97), IEEE Press, 1997, pp. 424-432.
    • (1997) Proc. Int'l Test Conf. (ITC 97) , pp. 424-432
    • Amason, D.1
  • 8
    • 0032116597 scopus 로고    scopus 로고
    • Test development for second-generation ColdFire microprocessors
    • July-Sept
    • D. Amason et al., "Test Development for Second-Generation ColdFire Microprocessors," IEEE Design & Test, vol. 15, no. 3, July-Sept. 1998, pp. 70-76.
    • (1998) IEEE Design & Test , vol.15 , Issue.3 , pp. 70-76
    • Amason, D.1
  • 9
    • 0033317235 scopus 로고    scopus 로고
    • The testability features of the 3rd generation ColdFire family of microprocessors
    • IEEE Press
    • A. Crouch et al., "The Testability Features of the 3rd Generation ColdFire Family of Microprocessors," Proc. Int'l Test Conf. (ITC 99), IEEE Press, 1999, pp. 913-922.
    • (1999) Proc. Int'l Test Conf. (ITC 99) , pp. 913-922
    • Crouch, A.1
  • 10
    • 0034481914 scopus 로고    scopus 로고
    • The testability features of the MCF5407 containing the 4th generation ColdFire microprocessor core
    • IEEE Press
    • T. McLaurin and F. Frederick, "The Testability Features of the MCF5407 Containing the 4th Generation ColdFire Microprocessor Core," Proc. Int'l Test Conf. (ITC 00), IEEE Press, 2000, pp. 151-159.
    • (2000) Proc. Int'l Test Conf. (ITC 00) , pp. 151-159
    • McLaurin, T.1    Frederick, F.2
  • 11
    • 0034476399 scopus 로고    scopus 로고
    • On-the-shelf core pattern methodology for ColdFire microprocessor cores
    • IEEE Press
    • T. McLaurin and J. Potter, "On-the-Shelf Core Pattern Methodology for ColdFire Microprocessor Cores," Proc. Int'l Test Conf. (ITC 00), IEEE Press, 2000, pp. 1100-1107.
    • (2000) Proc. Int'l Test Conf. (ITC 00) , pp. 1100-1107
    • McLaurin, T.1    Potter, J.2
  • 12
    • 0034476037 scopus 로고    scopus 로고
    • Optimization trade-offs for vector volume and test power
    • IEEE Press
    • B. Pouya and A. Crouch, "Optimization Trade-Offs for Vector Volume and Test Power," Proc. Int'l Test Conf. (ITC 00), IEEE Press, 2000, pp. 873-881.
    • (2000) Proc. Int'l Test Conf. (ITC 00) , pp. 873-881
    • Pouya, B.1    Crouch, A.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.