Multiple scan tree design with test vector modification

Proceedings of the Asian Test Symposium

Volumn , Issue , 2004, Pages 76-81

  Miyase, Kohei ^a   Kajihara, Seiji ^a   Reddy, Sudhakar M ^b  

^a KYUSHU INSTITUTE OF TECHNOLOGY   (Japan)

^b University of Iowa   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MULTIPLE SCAN DESIGNS; SCAN CHAINS; SCAN TREES; TEST VECTOR MODIFICATION;

BENCHMARKING; DATA REDUCTION; ENCODING (SYMBOLS); FLIP FLOP CIRCUITS; MICROPROCESSOR CHIPS; VECTORS;

TREES (MATHEMATICS);

EID: 13244295353     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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