Reducing test application time by scan flip-flops sharing

IEE Proceedings: Computers and Digital Techniques

Volumn 147, Issue 1, 2000, Pages 42-48

  Chang, S C ^a   Lee, K J ^a   Wu, Z Z ^b   Jone, W B ^b  

^a NATIONAL CHUNG CHENG UNIVERSITY   (Taiwan)

^b NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; CONSTRAINT THEORY; DESIGN FOR TESTABILITY; FLIP FLOP CIRCUITS; LOGIC CIRCUITS;

AUTOMATIC TEST PATTERN GENERATION; CIRCUIT UNDER TEST; SCAN BASED DESIGN;

INTEGRATED CIRCUIT TESTING;

EID: 0033902093     PISSN: 13502387     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cdt:20000188     Document Type: Article

References (20)

1. COURJON, II.'Scan desien in the Philips ASIC test environment'. Euro ASIC, May 1990, France, pp. 370-375
2. FUNATSU, S.KAWAI, M.and YAMADA, A.'Scan design at NEC', IEEE DCS. Test Comput.1989, 6, (3), pp. 50-57
3. HAGIHARA, Y.OHKUBO, C, OKAMOTO, F.YAMADA, H.TAKADA, M.and ENOMOTO, T.'Design for testability in a 200MFLOPS vector pipelined processor (VPP)-ULSI'. Proc. of First Asian Test Symposium, November, 1992, pp. 223-228
4. POWELL, T.J.HWANG, F.and JOHNSON, B.'Testability features in the TMS 370 family of microcomputers'. Proc. of New Frontiers in Testing ITC, September 1988, pp. 153-160
5. GOEL, P.and ROSALES, B.C.Test generation and dynamic compaction of tests'. ITC, June 1979, pp. 189-192
6. POMERANZ, I.'COMPACTEST: A method to generate compact test sets for combinational circuits'. ITC, October 1991, pp. 194-203
7. NARAYANAN, S.'Configuring multiple scan chains for minimum test time'. ICCAD, October 1992, pp. 4-8
8. NARAYANAN, S.and BREUER, M.A.'Asynchronous multiple scan chains'. Proc. of 13th IEEE VLSI Test Symposium, April 1995, pp. 270276
9. NARAYANAN, S.GUPTA, R.and BREUER, M.A.'Optimal configuring of multiple scan chains'. IEEE Trans. Comput.1993
10. YE, B.ZHENG, Z.HU, J.and LI, W.'Testability design with multiple scan chains'. Proc. of 4th International Conference on Solid-Slate and 1C Technology, October 1995, pp.,637-639
11. BHATIA, S.and JHA, N.'Synthesis for parallelsScan: Applications to partials Scan and robust path-delay fault testability'. TCAD, Feb. 1996, pp. 228-243
12. BLEEKER, H.'Boundary-scan test: a practical approach' (Kluwer Academic Publishers, 1993)
13. HRONIK, S.'Industry acceptance of boundary scan'. Proc. of WESCON, 1994, pp. 518-524
14. MAUNDER, C.M.and TULLOS, R.E.'The test access port and boundary-scan architecture' (IEEE Computer Society Press, 1990)
15. OSSEIRAN, A.'Test standards (with Focus on IEEE1149.1)'. Proc. of 38th Midwest Symposium on Circuits and System, August 1995, 2, pp. 708-711
16. LEE, K.J.CHEN, J.J.and HUANG, C.H.'Using a single input to support multiple scan chains'. Proceedinas of ICCAD, November 1998, pp. 74-78
17. ABRAMOVJCI, M.BREUER, M.A.and FRIEDMAN, A.D.'Digital systems testing and testable design'. ITC Conference, pp. 476-480
18. JONE, V.B'.Kand PAPACHRISTOU, C.A.'A coordinate circuit partitioning and test generation method for pseudo-exhaustive testing of VLSI circuits', IEEE Trans. CAD, 1995, 14, (3), pp. 374-384
19. SRINIVASSAN, R.GUPTA, S.K.and BREUER, M.A.'An efficient partitioning strategy for pseudo-exhaustive testing'. Proc. of ACM/IEEE DAC, October, 1993, pp. 242-248
20. BRAYTON, R.K.RUDELL, R.SANGIOVANNI-VINCENTELLI, A.and WANG,' A.R.'MIS: Multi-level interactive locic optimization system', IEEE Trans.CAD-6, (6), 1987, pp. 1062-1081