A cost-effective scan architecture for scan testing with non-scan test power and test application cost

Proceedings - Design Automation Conference

Volumn , Issue , 2003, Pages 744-747

  Xiang, Dong ^a   Gu, Shan ^a   Sun, Jia Guang ^a   Wu, Yu Liang ^b  

^a TSINGHUA UNIVERSITY   (China)

^b CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

Author keywords

Algorithms and Reliability

Indexed keywords

ALGORITHMS; COST EFFECTIVENESS; SEQUENTIAL CIRCUITS; VECTORS;

SCAN TESTING;

FLIP FLOP CIRCUITS;

EID: 0042134650     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/775832.776022     Document Type: Conference Paper

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