A method of static test compaction based on don't care identification

Proceedings - 1st IEEE International Workshop on Electronic Design, Test and Applications, DELTA 2002

Volumn , Issue , 2002, Pages 392-395

  Miyase, Kohei ^a   Kajihara, Seiji ^a   Reddy, Sudhakar M ^b  

^a KYUSHU INSTITUTE OF TECHNOLOGY   (Japan)

^b UNIVERSITY OF IOWA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS;

BENCHMARK CIRCUIT; DON'T-CARES; INPUT VALUES; STATIC TEST COMPACTION; TEST COMPACTION; TEST SETS;

COMPACTION;

EID: 0142096046     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DELTA.2002.994657     Document Type: Conference Paper

References (9)

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3. S. Kajihara, I. Pomeranz, K. Kinoshita and S. M. Reddy, "Cost Effective Generation of Minimal Test Sets for Stuck at Faults in Combinational Logic Circuits", IEEE Trans. on Computer-Aided Design, 1995, pp. 1496.
4. S. Kajihara, and K. K. Saluja "On Test Pattern Compaction Using Random Pattern Fault Simulation", 11th IEE International Conference on VLSI Design, Jan. 1998, pp. 464-469.
5. M. Schulz et al., "SOCRATES: A Highly Efficient Automatic Test Pattern Generation System", IEEE Trans. on CAD., Jan. 1988, pp. 126-137.
6. I. Hamzaoglu and J. H. Patel, "Test Set Compaction Algorithms for Combinational Circuits", ICCAD, Nov. 1998, pp. 283-288.
7. L. N. Reddy, I. Pomeranz, and S. M. Reddy, "ROTCO: A Reverse Order Test Compaction Technique", 1992 IEEE EURO-ASIC Conference, 1992, pp. 189-194.
8. J.-S. Chang and C.-S. Lin, "Test Set Compaction for Combinational Circuits", IEEE Trans. on Computer-Aided Design, Nov. 1995, pp. 1370-1378.
9. S. Kajihara, K. Miyase, "On Identifying Don't Care Inputs of Test Patterns for Combinational Circuits", ICCAD-2001, Nov. 2001.