Efficient BIST TPG design and test set compaction via input reduction

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 17, Issue 8, 1998, Pages 692-705

  Chen, Chih Ang ^a,b   Gupta, Sandeep K ^a  

^a University of Southern California   (United States)

^b Equator Technologies Inc   (United States)

Author keywords

Built in self test; Pseudoexhaustive testing; Scan chain design; Test pattern generators; Test set compaction

Indexed keywords

BUILT-IN SELF TEST; COMPUTER AIDED NETWORK ANALYSIS;

PSEUDOEXHAUSTIVE TESTING; SCAN CHAIN DESIGN; TEST PATTERN GENERATORS; TEST SET COMPACTION;

COMPUTER AIDED LOGIC DESIGN;

EID: 0032139116     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.712101     Document Type: Article

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