Reconfiguration technique for reducing test time and test data volume in Illinois Scan Architecture based designs

Proceedings of the IEEE VLSI Test Symposium

Volumn 2002-January, Issue , 2002, Pages 9-15

  Pandey, A R ^a,b   Patel, J H ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^b ADVANCED MICRO DEVICES   (United States)

Author keywords

Automatic test pattern generation; Circuit testing; Clocks; Computer architecture; Costs; Hardware; Integrated circuit manufacture; Integrated circuit testing; Semiconductor device testing; Very large scale integration

Indexed keywords

CLOCKS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COSTS; HARDWARE; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUIT TESTING; INTEGRATED CIRCUITS; INTEGRATION TESTING; MANUFACTURE; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE TESTING; SEMICONDUCTOR DEVICES; SEQUENTIAL CIRCUITS; VLSI CIRCUITS;

CIRCUIT TESTING; HARDWARE IMPLEMENTATIONS; MANUFACTURING COST; NUMBER OF CLOCK CYCLES; SCAN ARCHITECTURE; TEST APPLICATIONS; TEST-DATA VOLUME; TRANSISTOR COUNT;

AUTOMATIC TEST PATTERN GENERATION;

EID: 84948422015     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2002.1011104     Document Type: Conference Paper

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