-
1
-
-
0030685592
-
'Testing embedded cores using partial isolation rings'
-
May
-
Touba N., and Pouya, B.: 'Testing embedded cores using partial isolation rings'. Proc. VLSI Test Symp. (VTS), May 1997, pp. 10-16
-
(1997)
Proc. VLSI Test Symp. (VTS)
, pp. 10-16
-
-
Touba, N.1
Pouya, B.2
-
2
-
-
0032320505
-
'A structured and scalable mechanism for test access to embedded reusable cores'
-
Marinissen, E., Arendsen, R., Bos, G., Dingemanse, H., Lousberg, M., and Wouters, C.: 'A structured and scalable mechanism for test access to embedded reusable cores'. Proc. Int. Test Conf. (ITC), 1998, pp. 284-293
-
(1998)
Proc. Int. Test Conf. (ITC)
, pp. 284-293
-
-
Marinissen, E.1
Arendsen, R.2
Bos, G.3
Dingemanse, H.4
Lousberg, M.5
Wouters, C.6
-
3
-
-
0034483643
-
'An ILP formulation to optimize test access mechanism in SoC testing'
-
October
-
Nourani, M., and Papachristou, C.: 'An ILP formulation to optimize test access mechanism in SoC testing'. Proc. Int. Test Conf. (ITC), October 2000, pp. 902-910
-
(2000)
Proc. Int. Test Conf. (ITC)
, pp. 902-910
-
-
Nourani, M.1
Papachristou, C.2
-
6
-
-
0003850954
-
'Digital Integrated Circuits'
-
(Prentice Hall)
-
Rabaey, J.: 'Digital Integrated Circuits' (Prentice Hall, 1996)
-
(1996)
-
-
Rabaey, J.1
-
7
-
-
0029226463
-
'Efficient power estimation for highly correlated input streams'
-
Marculescu, R., Marculescu, D., and Pedram, M.: 'Efficient power estimation for highly correlated input streams'. Proc. Conf. on Design Automation, 1995, pp. 628-634
-
(1995)
Proc. Conf. on Design Automation
, pp. 628-634
-
-
Marculescu, R.1
Marculescu, D.2
Pedram, M.3
-
8
-
-
0030107209
-
'Fast power estimation of large circuits'
-
Sclmeider, P., Schlichtmann, U., and Wurth, B.: 'Fast power estimation of large circuits', IEEE Design Test Comput., 1996, pp. 70-78
-
(1996)
IEEE Design Test Comput.
, pp. 70-78
-
-
Sclmeider, P.1
Schlichtmann, U.2
Wurth, B.3
-
9
-
-
0029724652
-
'A symbolic simulation approach in resolving signals' correlation'
-
Dunoyer, J., Abdallah, N., and Bazargan, P.: 'A symbolic simulation approach in resolving signals' correlation'. Proc. Symp. on Simulation, 1996, pp. 203-211
-
(1996)
Proc. Symp. on Simulation
, pp. 203-211
-
-
Dunoyer, J.1
Abdallah, N.2
Bazargan, P.3
-
10
-
-
0030650441
-
'Estimation of average switching activity in combinational logic circuits using symbolic simulation'
-
Monterio, J., Devadas, S., Ghosh, A., Keutzer, K., and White, J.: 'Estimation of average switching activity in combinational logic circuits using symbolic simulation', IEEE Trans. Comput.-Aided Des. 1997, 16, (1), pp. 121-127
-
(1997)
IEEE Trans. Comput.-Aided Des.
, vol.16
, Issue.1
, pp. 121-127
-
-
Monterio, J.1
Devadas, S.2
Ghosh, A.3
Keutzer, K.4
White, J.5
-
11
-
-
0029544855
-
'Power estimation techniques for integrated circuits'
-
November
-
Najm, F.: 'Power estimation techniques for integrated circuits'. Proc. Int. Conf. on Computer-Aided Design, November 1995, pp. 492-499
-
(1995)
Proc. Int. Conf. on Computer-Aided Design
, pp. 492-499
-
-
Najm, F.1
-
12
-
-
0034292688
-
'Test scheduling for core-based systems using mixed-integer linear programming'
-
Chakrabarty, K.: 'Test scheduling for core-based systems using mixed-integer linear programming', IEEE Trans. Comput.-Aided Des., 2000, 19, pp. 1163-1174
-
(2000)
IEEE Trans. Comput.-Aided Des.
, vol.19
, pp. 1163-1174
-
-
Chakrabarty, K.1
-
13
-
-
0033684205
-
'Self-test methodology for at-speed test of crosstalk in chip interconnects
-
Bai, X., Dey, S., and Rajski, J.: 'Self-test methodology for at-speed test of crosstalk in chip interconnects. Proc. Conf. on Design Automation (DAC), 2000, pp. 619-624
-
(2000)
Proc. Conf. on Design Automation (DAC)
, pp. 619-624
-
-
Bai, X.1
Dey, S.2
Rajski, J.3
-
14
-
-
0034846665
-
'Built-In Self-Test for Signal Integrity'
-
Las Vegas, Nevada, June
-
Nourani, M., and Attarha, A.: 'Built-In Self-Test for Signal Integrity'. Proc. 38th Conf. on Design Automation (DAC), Las Vegas, Nevada, June 2001, pp. 792-797
-
(2001)
Proc. 38th Conf. on Design Automation (DAC)
, pp. 792-797
-
-
Nourani, M.1
Attarha, A.2
-
15
-
-
0142237005
-
'Integrated test scheduling, test parallelisation and TAM design'
-
November
-
Larsson, E., Arvidsson, K., Fujiwara, H., and Peng, Z.: 'Integrated test scheduling, test parallelisation and TAM design'. Proc. 11th Asian Test Symp., November 2002, pp. 397-404
-
(2002)
Proc. 11th Asian Test Symp.
, pp. 397-404
-
-
Larsson, E.1
Arvidsson, K.2
Fujiwara, H.3
Peng, Z.4
-
16
-
-
84942925785
-
'An efficient approach to SoC wrapper design, TAM configuration and test scheduling'
-
May
-
Pouget, J., Larsson, E., Peng, Z., Flottes, M., and Rouzeyre, B.: 'An efficient approach to SoC wrapper design, TAM configuration and test scheduling'. Proc. 8th IEEE European Test Workshop, May 2003, pp. 51-56
-
(2003)
Proc. 8th IEEE European Test Workshop
, pp. 51-56
-
-
Pouget, J.1
Larsson, E.2
Peng, Z.3
Flottes, M.4
Rouzeyre, B.5
-
17
-
-
0031163752
-
'Scheduling tests for VLSI systems under power constraints'
-
Chou, R., Saluja, K., and Agrawal, V.: 'Scheduling tests for VLSI systems under power constraints', IEEE Trans. Very Large Scale Integr., 1997, 5, (2), pp. 175-185
-
(1997)
IEEE Trans. Very Large Scale Integr.
, vol.5
, Issue.2
, pp. 175-185
-
-
Chou, R.1
Saluja, K.2
Agrawal, V.3
-
18
-
-
0004959811
-
'List scheduling and tree-growing technique in power-constrained block test scheduling'
-
Muresan, V., Wang, X., Muresan, V., and Vladutiu, M.: 'List scheduling and tree-growing technique in power-constrained block test scheduling'. Digest of European Test Workshop, 2000, pp. 27-32
-
(2000)
Digest of European Test Workshop
, pp. 27-32
-
-
Muresan, V.1
Wang, X.2
Muresan, V.3
Vladutiu, M.4
-
19
-
-
0034995151
-
'Precedence-based, pre-emptive, and power-constrained test scheduling for system-on-a-chip'
-
Iyengar, V., and Chakrabarty, K.: 'Precedence-based, pre-emptive, and power-constrained test scheduling for system-on-a-chip'. Proc. Symp. on VLSI Test, 2001, pp. 368-374
-
(2001)
Proc. Symp. on VLSI Test
, pp. 368-374
-
-
Iyengar, V.1
Chakrabarty, K.2
-
20
-
-
0035699333
-
'A gated clock scheme for low-power scan testing of logic ICs or embedded cores'
-
November
-
Bonhomme, Y., Girard, P., Guiller, L., Landrault, C., and Pravossoudovitch, S.: 'A gated clock scheme for low-power scan testing of logic ICs or embedded cores'. Proc. 10th Asian Test Symp., November 2001, pp. 253-258
-
(2001)
Proc. 10th Asian Test Symp.
, pp. 253-258
-
-
Bonhomme, Y.1
Girard, P.2
Guiller, L.3
Landrault, C.4
Pravossoudovitch, S.5
-
21
-
-
84887471573
-
'Reducing test power during test using programmable scan chain disable'
-
29-31 January
-
Sankaralingam, R., and Touba, N.: 'Reducing test power during test using programmable scan chain disable'. Proc. IEEE Int. Workshop on Electronic Design, Test and Applications, 29-31 January 2002, pp. 159-163
-
(2002)
Proc. IEEE Int. Workshop on Electronic Design, Test and Applications
, pp. 159-163
-
-
Sankaralingam, R.1
Touba, N.2
-
22
-
-
84948443429
-
'Test power reduction through minimisation of scan chain transitions'
-
April
-
Sinanoglu, O., Bayraktaroglu, I., and Oralloglu, A.: 'Test power reduction through minimisation of scan chain transitions'. Proc. 20th IEEE VLSI Test Symp., April 2002, pp. 166-171
-
(2002)
Proc. 20th IEEE VLSI Test Symp.
, pp. 166-171
-
-
Sinanoglu, O.1
Bayraktaroglu, I.2
Oralloglu, A.3
-
23
-
-
0036603477
-
'Multiple scan chains for power minimization during test application in sequential circuits'
-
Nicolici, N., and Al-Hashimi, B.: 'Multiple scan chains for power minimization during test application in sequential circuits', IEEE Trans. Comput., 2002, 51, (6), pp. 721-734
-
(2002)
IEEE Trans. Comput.
, vol.51
, Issue.6
, pp. 721-734
-
-
Nicolici, N.1
Al-Hashimi, B.2
-
24
-
-
84943549327
-
Test resource partitioning and optimization for SoC designs'
-
May
-
Larsson, E., and Fujiwara, H.: Test resource partitioning and optimization for SoC designs'. Proc. of 21st IEEE Symp. on VLSI Test, May 2003, pp. 319-324
-
(2003)
Proc. of 21st IEEE Symp. on VLSI Test
, pp. 319-324
-
-
Larsson, E.1
Fujiwara, H.2
-
25
-
-
0036810725
-
'Power profile manipulation: A new approach for reducing test application time under power constraints'
-
Rosinger, P., Al-Hashimi, B., and Nicolici, N.: 'Power profile manipulation: a new approach for reducing test application time under power constraints', IEEE Trans. Computer-Aided Des. Integr. Circuits Syst., 2002, 21, (10), pp. 1217-1225
-
(2002)
IEEE Trans. Computer-Aided Des. Integr. Circuits Syst.
, vol.21
, Issue.10
, pp. 1217-1225
-
-
Rosinger, P.1
Al-Hashimi, B.2
Nicolici, N.3
-
27
-
-
0035701545
-
'Resource allocation and test scheduling for concurrent test of core-based SoC design'
-
Huang, Y., Cheng, W., Tsai, C., Mukherjee, N., Samman, O., Zaidan, Y., and Reddy, S.: 'Resource allocation and test scheduling for concurrent test of core-based SoC design'. Proc. Asian Test Symp., 2001, pp. 265-270
-
(2001)
Proc. Asian Test Symp.
, pp. 265-270
-
-
Huang, Y.1
Cheng, W.2
Tsai, C.3
Mukherjee, N.4
Samman, O.5
Zaidan, Y.6
Reddy, S.7
-
28
-
-
0036446177
-
'Optimal core wrapper width selection and SoC test scheduling based on 3-D bin packing algorithm'
-
October
-
Huang, Y., Reddy, S., Cheng, W., Reuter, P., Mukherjee, N., Tsai, C., Samman, O., and Zaidan, Y.: 'Optimal core wrapper width selection and SoC test scheduling based on 3-D bin packing algorithm'. Proc. Int. Test Conf., October 2002, pp. 74-82
-
(2002)
Proc. Int. Test Conf.
, pp. 74-82
-
-
Huang, Y.1
Reddy, S.2
Cheng, W.3
Reuter, P.4
Mukherjee, N.5
Tsai, C.6
Samman, O.7
Zaidan, Y.8
-
29
-
-
0036047771
-
'Wrapper/TAM co-optimisation, constraint-driven test scheduling, and tester data volume reduction for SoCs'
-
June
-
Iyengar, V., Chakrabarty, K., and Marinissen, E.: 'Wrapper/TAM co-optimisation, constraint-driven test scheduling, and tester data volume reduction for SoCs'. Proc. 39th Conf. on Design Automation, June 2002, pp. 685-690
-
(2002)
Proc. 39th Conf. on Design Automation
, pp. 685-690
-
-
Iyengar, V.1
Chakrabarty, K.2
Marinissen, E.3
-
30
-
-
0344550538
-
'Power-Time trade off in test scheduling for SoC'
-
October
-
Nourani, M., and Chin, J.: 'Power-Time trade off in test scheduling for SoC'. Proc. Int. Conf. on Computer Design, October 2003, pp. 548-553
-
(2003)
Proc. Int. Conf. on Computer Design
, pp. 548-553
-
-
Nourani, M.1
Chin, J.2
-
32
-
-
0004247897
-
'Optimization: Foundations and applications'
-
(Wiley)
-
Miller, R.: 'Optimization: Foundations and applications' (Wiley, 2000)
-
(2000)
-
-
Miller, R.1
-
33
-
-
0003982971
-
'Numerical optimization'
-
(Springer)
-
Nocedal, J., and Wright, S.: 'Numerical optimization' (Springer, 1999)
-
(1999)
-
-
Nocedal, J.1
Wright, S.2
|