Self-test methodology for at-speed test of crosstalk in chip interconnects

Proceedings - Design Automation Conference

Volumn , Issue , 2000, Pages 619-624

  Bai, Xiaoliang ^a   Dey, Sujit ^a   Rajski, Janusz ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b MENTOR GRAPHICS CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER HARDWARE DESCRIPTION LANGUAGES; CROSSTALK; INTERCONNECTION NETWORKS;

CHIP INTERCONNECTS; MAXIMAL AGGRESSOR FAULT MODEL; SYSTEM-ON-CHIPS;

BUILT-IN SELF TEST;

EID: 0033684205     PISSN: 0738100X     EISSN: None     Source Type: Journal    
DOI: 10.1109/DAC.2000.855387     Document Type: Article

References (12)

1. H Zhou D. F. Wang Global Routing with Crosstalk Constaints Proceedings 1998 design and Automation conference 35 DAC 374 377 Proceedings 1998 design and Automation conference 35 DAC 1998
2. Z. Chen I. Koren Crosstalk Minimization in Three-Layer HVH Channel Routing Proceeding IEEE International Symposium on Defect and Fault Tolerance in VLSI System 38 42 Proceeding IEEE International Symposium on Defect and Fault Tolerance in VLSI System 1997
3. P. Nordholz D. Treytnar J. Otterstedt H. Grabinski D. Niggemeyer T. W. Williams Signal Integrity Problems in Deep Submicron arising from Interconnects between Cores Proceedings IEEE VLSI Test Symposium 28 33 Proceedings IEEE VLSI Test Symposium 1998
4. K. Rahmat J. Neves J. Lee Methods for calculating coupling noise in early design: a comparative analysis Proceeding International Conference on Computer Design VLSI in Computers and Processors 76 81 Proceeding International Conference on Computer Design VLSI in Computers and Processors 1998
5. H. Kawaguchi T. Sakurai Delay and Noise Formulas for Capacitively Coupled Distributed RC Lines Proceedings of the Asian and South Pacific Design Automation Conference 35 43 Proceedings of the Asian and South Pacific Design Automation Conference 1998
6. International Technology Roadmap for Semiconductor 1999 Semiconductor Industry Association (SIA)
7. K. T. Lee C. Nordquist J. Abraham Pattern generation for Crosstalk Glitches in Digital Circuits Proceedings IEEE VLSI Test Symposium 34 39 Proceedings IEEE VLSI Test Symposium 1998
8. W. Chen S. K. Gupta M. A. Breuer Test Generation in VLSI Circuits for Crosstalk Noise Proceedings IEEE International Test Conference 641 650 Proceedings IEEE International Test Conference 1998
9. C. Inacio The Carnegie Mellon Synthesizable Digital Signal Processor Core 1999 The CMU DSP Team
10. Leonardo Spectrum, V1999.1d CA, Fremont Exemplar Logic Inc.
11. ModeSim EE Vsim 5.3a Simulator OR, Portland Model Technology Inc.
12. M. Cuviello S. Dey X. Bai Y. Zhao Fault Modeling and Simulation for Crosstalk in System-On-Chip Interconnects Proceedings of the International Conference on Computer-Aided Design (ICCAD) 297 303 Proceedings of the International Conference on Computer-Aided Design (ICCAD) 1999