Integrated test scheduling, test parallelization and TAM design

Proceedings of the Asian Test Symposium

Volumn 2002-January, Issue , 2002, Pages 397-404

  Larsson, E ^a,b   Arvidsson, K ^b   Fujiwara, H ^a   Peng, Z ^b  

^a NARA INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

^b LINKÖPING UNIVERSITY   (Sweden)

Author keywords

Benchmark testing; Computational efficiency; Computer industry; Costs; Job shop scheduling; Logic testing; Power system interconnection; Power system modeling; Routing; System testing

Indexed keywords

BENCHMARKING; COMPUTATION THEORY; COMPUTATIONAL EFFICIENCY; COSTS; INTEGRATED CIRCUIT TESTING; OPTIMIZATION; SCHEDULING;

BENCHMARK TESTING; COMPUTER INDUSTRY; LOGIC TESTING; POWER SYSTEM INTERCONNECTION; POWER SYSTEM MODEL; ROUTING; SYSTEM TESTING;

JOB SHOP SCHEDULING;

EID: 0142237005     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ATS.2002.1181744     Document Type: Conference Paper

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