Fast power estimation of large circuits

IEEE Design and Test of Computers

Volumn 13, Issue 1, 1996, Pages 70-78

  Schneider, Peter H ^a   Schlichtmann, Ulf ^a,b,c,d,e   Wurth, Bernd ^a,f  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

^b SIEMENS AG   (Germany)

^c Siemens Semiconductor Group

^d IBM JAPAN LTD   (Japan)

^e Microlectron Ctr of North Carolina   (United States)

^f UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPROXIMATION THEORY; BOOLEAN FUNCTIONS; ENERGY UTILIZATION; MARKOV PROCESSES; OPTIMIZATION; PROBABILITY; RECURSIVE FUNCTIONS;

CONCURRENT TRANSITION; INTERNAL SIGNAL TRANSITION PROBABILITIES; POWER ESTIMATION; RECONVERGENCE REGIONS; REDUCED ORDERED BINARY DECISION DIAGRAMS (ROBDD); TEMPORAL DEPENDENCE; TRANSITION FUNCTION;

COMBINATORIAL CIRCUITS;

EID: 0030107209     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.485785     Document Type: Article

References (10)

1. F.N. Najm, "Transition Density, A Stochastic Measure of Activity in Digital Circuits," Proc. 28th Design Automation Conf., IEEE Computer Society Press, Los Alamitos, Calif., 1991, pp. 644-649.
2. A. Ghosh et al., "Estimation of Average Switching Activity in Combinational and Sequential Circuits," Proc. 29th Design Automation Conf., IEEE CS Press, 1992, pp. 253-259.
3. B. Kapoor, "Improving the Accuracy of Circuit Activity Measurement," Proc. 31st Design Automation Conf., IEEE CS Press, 1994, pp. 734-739.
4. T.-L. Chou, K. Roy, and S. Prasad, "Estimation of Circuit Activity Considering Signal Correlations and Simultaneous Switching," Proc. Int'l Conf. Computer-Aided Design, IEEE CS Press, 1994, pp. 300-309.
5. R. Marculescu, D. Marculescu, and M. Pedram, "Switching Activity Analysis Considering Spatiotemporal Correlations," Proc. Int'l Conf. Computer-Aided Design, IEEE CS Press, 1994, pp. 294-299.
6. P.H. Schneider and U. Schlichtmann, "Decomposition of Boolean Function for Low Power Based on a New Power Estimation Technique," Proc. IEEE Int'l Workshop on Low Power Design, IEEE, Piscataway, N.J., 1994, pp. 123-128.
7. R.E. Bryant, "Graph-Based Algorithms for Boolean Function Manipulation," IEEE Trans. Computers, Vol. C-35, No. 8, Aug. 1986, pp. 677-691.
8. L. Glasser and D. Dobberpuhl, The Design and Analysis of VLSI Circuits, Addison-Wesley, Reading, Mass., 1985.
9. F. Maamari and J. Rajski, "A Reconvergent Fanout Analysis for Efficient Exact Fault Simulation," Proc. 18th Int'l Symp. Fault-Tolerant Computing, IEEE CS Press, 1988, pp. 122-127.
10. E.M. Sentovich et al., "Sequential Circuit Design Using Synthesis and Optimization," Proc. IEEE Int'l Conf. Computer Design, IEEE CS Press, 1992, pp. 328-333.