Testing for function and performance: towards an integrated processor validation methodology

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 16, Issue 1-2, 2000, Pages 29-48

  Bose, Pradip ^a,b,c,d  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b INDIAN INSTITUTE OF TECHNOLOGY   (India)

^c UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^d INDIAN STATISTICAL INSTITUTE   (India)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SIMULATION; COMPUTER TESTING; PERFORMANCE; PIPELINE PROCESSING SYSTEMS;

BOUNDS MODELING; INTEGRATED METHODOLOGY; MICROPROCESSOR TESTING; PERFORMANCE TEST CASES; PERFORMANCE VALIDATION; TEST GENERATION;

MICROCOMPUTERS;

EID: 0034139974     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/a:1008363921045     Document Type: Article

References (27)

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