Power-performance modeling and tradeo analysis for a high end microprocessor

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2008, Issue , 2001, Pages 126-136

  Brooks, David ^a   Martonosi, Margaret ^a   Wellman, John David ^b   Bose, Pradip ^b  

^a PRINCETON UNIVERSITY   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMMERCE; PRODUCT DESIGN;

ENERGY CHARACTERIZATION; HIGH-END MICROPROCESSORS; MICRO ARCHITECTURES; PERFORMANCE MODEL; POWER PERFORMANCE; POWER SIMULATION; PRODUCT FAMILIES; REFERENCE MODELING;

POWER MANAGEMENT;

EID: 0347345913     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-44572-2_10     Document Type: Conference Paper

References (13)

1. D. Brooks, V. Tiwari, and M. Martonosi. Wattch: A framework for architectural-level power analysis and optimizations. In Proceedings of the 27th Annual International Symposium on Computer Architecture, pages 83-94, June 2000.
2. T. Conte, K. Menezes, and S. Sathaye. A technique to determine power-efficient, high performance superscalar processors. In Proceedings of the 28th Hawaii Int'l Conference on System Science, 1995.
3. 2EST: A Thermal Enabled Multi-Model Power/Performance ESTimator. In Power Aware Computing Systems Workshop at ASPLOS-IX, Nov. 2000.
4. K. Diefendor. Power4 focuses on memory bandwidth. Microprocessor Report, pages 11-17, Oct. 6, 1999.
5. R. Gonzalez and M. Horowitz. Energy Dissipation in General Purpose Microprocessors. IEEE Journal of Solid-State Circuits, 31(9):1277-84, 1996.
6. U. Ko, P. Balsara, and A. Nanda. Energy optimization of multilevel cache architectures for RISC and CISC processors. IEEE Transactions on VLSI Systems, 6(2):299-308, June 1998.
7. C. Moore. The Power4 System Microarchitecture. Microprocessor Forum, Oct 2000.
8. M. Moudgill, P. Bose, and J. Moreno. Validation of Turandot, a fast processor model for microarchitecture exploration. In Proceedings of the IEEE International Performance, Computing, and Communications Conference (IPCCC), pages 451-457, Feb. 1999.
9. M. Moudgill, J. Wellman, and J. Moreno. Environment for PowerPC microarchitecture exploration. IEEE Micro, 19(3):9-14, May/June 1999.
10. Papers presented at: 1998 ISCA Workshop on Power-Driven Microarchitecture: http://www.cs.colorado.edu/grunwald/LowPowerWorkshop/agenda.html, 1998.
11. Papers presented at: 2000 ISCA Workshop on Complexity-Effective Design: http://www.ece.rochester.edu/albonesi/ced00.html, 2000.
12. N. Vijaykrishnan, M. Kandemir, M. Irwin, H. Kim, and W. Ye. Energy-driven integrated hardware-software optimizations using simple power. In Proc. of the 27th Int'l Symp. on Computer Architecture, June 2000.
13. V. Zyuban. Inherently lower-power high performance superscalar architectures. PhD thesis, University of Notre Dame, January 2000.