Increasing processor performance by implementing deeper pipelines

Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA

Volumn , Issue , 2002, Pages 25-34

  Sprangle, Eric ^a   Carmean, Doug ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; COMPUTER ARCHITECTURE; COMPUTER CONTROL; COMPUTER SIMULATION; MICROPROCESSOR CHIPS;

ON-CHIP CACHE MEMORIES;

PIPELINE PROCESSING SYSTEMS;

EID: 0036296819     PISSN: 08847495     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. The alpha 21264 microprocessor
2. A 0.18-um CMOS IA-32 microprocessor with a 4-GHz integer execution unit
3. A multigigahertz clocking scheme for the Pentium® 4 microprocessor
4. A 0.6 um BiCMOS processor with dynamic execution
5. Multiple-block ahead branch predictors
6. Alternative fetch and issue policies for the trace cache fetch mechanism
7. The future of wires