Balancing hardware intensity in microprocessor pipelines

IBM Journal of Research and Development

Volumn 47, Issue 5-6, 2003, Pages 585-598

  Zyuban, Victor ^a   Strenski, Philip N ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOUNDARY CONDITIONS; COMPUTER HARDWARE; DATA REDUCTION; ELECTRIC POTENTIAL; ELECTRIC POWER SYSTEMS; ENERGY DISSIPATION; ENERGY EFFICIENCY; LOGIC CIRCUITS; PIPELINE PROCESSING SYSTEMS; PROGRAM PROCESSORS;

CIRCUIT DOMAINS; HARDWARE INTENSITY; SUPPLY-VOLTAGE SCALING;

MICROPROCESSOR CHIPS;

EID: 0348017034     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.475.0585     Document Type: Review

References (19)

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