Environment for powerPC microarchitecture exploration

IEEE Micro

Volumn 19, Issue 3, 1999, Pages 15-25

  Moudgill, Mayan ^a   Wellman, John David ^b   Moreno, Jaime H ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b NONE

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; COMPUTATIONAL COMPLEXITY; COMPUTER AIDED SOFTWARE ENGINEERING; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; GENERAL PURPOSE COMPUTERS; PIPELINE PROCESSING SYSTEMS; PROGRAM COMPILERS; RESPONSE TIME (COMPUTER SYSTEMS); SYSTEMS ANALYSIS;

GENERAL PURPOSE MICROPROCESSOR; MICROARCHITECTURE EXPLORATION TOOLSET; POWERPC MICROARCHITECTURE; REGISTER TRANSFER LEVEL;

MICROPROCESSOR CHIPS;

EID: 0032683935     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/40.768496     Document Type: Article

References (7)

1. D. Burger and T.M. Austin, The SimpleScalar Tool Set, Version 2, Tech. Report No. 1342, Computer Sciences Dept, Univ. of Wisconsin, Madison, June 1997.
2. T. Diep and J.P. Shen, "VMW: A Visualization-Based Microarchitecture Workbench," Computer, Dec. 1995, pp. 57-64.
3. M. Reilly and J. Edmondson, "Performance Simulation of an Alpha Microprocessor," Computer, May 1998, pp. 50-58.
4. B. Cmelik and D. Keppel, "Shade: A Fast Instruction-Set Simulator for Execution Profiling," Fast Simulation of Computer Architectures, T. Conte and C. Gimarc, eds., Kluwer Academic, Norwell, Mass., 1995.
5. P. Bose et al., "Bounds-Based Loop Performance Analysis: Application to Validation and Tuning," Proc. IEEE Int'l Performance, Computing, and Communication Conf., IEEE Press, Piscataway, N.J., Feb. 1998, pp. 178-184.
6. B. Black and J.P. Shen, "Calibration of Microprocessor Performance Models," Computer, Vol. 31, No. 5, May 1998, pp. 59-65.
7. P. Emma, "Understanding Some Simple Performance Limits," IBM J. Research and Development, May/June 1997.