Power3: The next generation of PowerPC processors

IBM Journal of Research and Development

Volumn 44, Issue 6, 2000, Pages 873-884

  O'Connell, F P ^a   White, S W ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; BUFFER STORAGE; DATA REDUCTION; PERSONAL COMPUTERS; PROGRAM PROCESSORS; SUPERCOMPUTERS;

TECHNICAL COMPUTING;

MICROPROCESSOR CHIPS;

EID: 0034312318     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.446.0873     Document Type: Article

References (9)

1. The PowerPC Architecture: A Specification for a New Family of RISC Processors, Second Edition, C. May, E. Silha, R. Simpson, and H. Warren, Eds., Morgan Kaufmann Publishers, Inc., San Francisco, 1994.
2. Steve White and John Reysa, PowerPC and Power2: Technical Aspects of the New IBM RISC System/6000, First Edition, IBM Order No. SA23-2737-00, 1994, available through IBM branch offices.
3. T. C. Mowry, M. S. Lam, and A. Gupta, "Design and Evaluation of a Compiler Algorithm for Prefetching," Proceedings of the Fifth International Conference on Architectural Support for Programming Languages and Operating Systems, October 1992.
4. STREAM: Sustainable Memory Bandwidth in High Performance Computers, http://www.cs.virginia.edu/stream/.
5. Jack J. Dongarra, Iain S. Duff, Danny C. Sorensen, and Henk A. van der Vorst, Solving Linear Systems on Vector and Shared Memory Computers, Society for Industrial and Applied Mathematics, Philadelphia, 1991.
6. Engineering and Scientific Subroutine Library for AIX, Guide and Reference, IBM Order No. SA22-7272, 1998; available online at http: //www.rs6000.ibm.com/resource/aix_resource/sp_books/essl/.
7. LINPACK, http: //performance.netlib.org/performance/html/PDSbrowse.html.
8. The sPPM benchmark code README file, http: //www.lcse.umn.edu/research/sppm.
9. IBM Mathematical Acceleration SubSystem, http: //www.austin.ibm.com/resource/technology/MASS/.