A hybrid coding strategy for optimized test data compression

IEEE International Test Conference (TC)

Volumn , Issue , 2003, Pages 451-459

  Würtenberger, Armin ^a   Tautermann, Christofer S ^a   Hellebrand, Sybille ^a  

^a UNIVERSITY OF INNSBRUCK   (Austria)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BANDWIDTH; MICROPROCESSOR CHIPS; SIGNAL ENCODING;

HYBRID CODING;

DATA COMPRESSION;

EID: 0142246917     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (36)

1. M. Abramovici, M. Breuer, A. Friedman: Digital Systems Testing and Testable Design; New York: Computer Science Press (W. H. Freeman and Co.), 1990
2. F. Brglez et al.: Accelerated ATPG and fault grading via testability analysis; Proc. IEEE Int. Symp. on Circuits and Systems, Kyoto, Japan, 1985
3. F. Brglez, D. Bryan and K. Kozminski: Combinational Profiles of Sequential Benchmark Circuits; Proc. IEEE Int. Symp. on Circuits and Systems, 1989, Portland, OR, USA, pp. 1929-1934
4. J. Capon: A Probabilistic Model for Run-Length Coding of Pictures; IRE Trans. on Information Theory, December 1959, pp. 157-163
5. A. Chandra, K. Chakrabarty: System-on-a-chip test data compression and decompression architectures based on Golomb codes; IEEE Trans. on CAD of Integrated Circuits and Systems, Vol. 20, No. 3, March 2001, pp. 355-368
6. th VLSI Test Symp., Marina Del Rey, CA, USA, 2001, pp. 42-43
7. A. Chandra, K. Chakrabarty: Test Resource Partitioning and Reduced Pin-Count Testing Based on Test Data Compression; Proc. 2002 Design and Test in Europe, Paris, France, March 4-8, 2002, pp. 598-603
8. A. Chandra, K. Chakrabarty: Low Power Scan Testing and Test Data Compression for System-on-a-Chip; IEEE Trans. on CAD of Integrated Circuits and Systems, Vol. 21, No. 5, May 2002, pp. 597-604
9. A. Chandra, K. Chakrabarty: Test Data Compression and Decompression Based on Internal Scan Chains and Golomb Coding; IEEE Trans. on CAD of Integrated Circuits and Systems, Vol. 21, No. 6, June 2002, pp. 715-722
10. A. Chandra, K. Chakrabarty: Reduction of SoC Test Data Volume, Scan Power and Testing Time Using Alternating Run-length Codes; Proc. ACM/IEEE Int. Design Autom. Conf., 2002, New Orleans, LA, USA, pp. 673-678
11. th IEEE VLSI Test Symp., Monterey, CA, USA, 2002, pp. 91-96
12. D. E. Goldberg, Genetic Algorithms in Search, Optimization, and Machine Learning; Reading, MA: Addison-Wesley, 1989
13. S. W. Golomb: Run-Length Encodings; IEEE Trans. on Information Theory, July 1966, pp. 399-401
14. P. T. Gonciari, B. M. Al-Hashimi, N. Nicolici: Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression / Decompression; Proc. 2002 Design and Test in Europe, Paris, France, March 4-8, 2002, pp. 604-611
15. S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, and B. Courtois: Built-in Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers; IEEE Trans. on Comp., Vol. 44, No.2, February 1995, pp. 223-233
16. S. Hellebrand, B. Reeb, S. Tarnick, H.-J. Wunderlich: Pattern Generation for a Deterministic BIST Scheme; Proc. IEEE/ACM Int. Conf. on CAD-95, San Jose, CA, USA, November 1995, pp. 88-94
17. S. Hellebrand, A. Würtenberger: Alternating Run-Length Coding - A Technique for Improved Test Data Compression; IEEE Int. Workshop on Test Resource Partitioning, Baltimore, MD, USA, October 2002
18. th IEEE VLSI Test Symp., Monterey, CA, USA, 1998, pp. 62-69
19. A. Jas, N. A. Touba: Test Vector Decompression via Cyclical Scan Chains and Its Application to Testing Core-Based Designs; Proc. IEEE Int. Test Conf., Washington, DC, USA, 1998, pp. 458-464
20. th IEEE VLSI Test Symp., Dana Point, CA, USA, 1999, pp. 114-120
21. th VLSI Test Symp., Marina Del Rey, CA, USA, 2001, pp. 9-14
22. G. Kiefer, H. Vranken, E. J. Marinissen, H.-J. Wunderlich: Application of Deterministic Logic BIST on Industrial Circuits; Proc. IEEE Int. Test Conf., ITC 2000, Atlantic City, NJ, USA, October 3 - 5, 2000
23. S. Kirkpatrick, C. D. Gelatt Jr., M. P. Vecchi: Optimization by Simulated Annealing; Science, Vol. 220, No. 4598, May 1983, pp. 671 - 680
24. B. Koenemann: LFSR-Coded Test Patterns for Scan Designs; Proc. Europ. Test Conf., Munich, Germany, 1991, pp. 237-242
25. P. J. M. Laarhoven, E. H. L. Aarts: Simulated Annealing: Theory and Applications; Dordrecht, Boston, Lancaster, Tokyo: Verlag D. Reidel Publishing Company, 1987
26. Hua-Guo Liang, S. Hellebrand, H.-J. Wunderlich: Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST; Proc. IEEE Int. Test Conf., Baltimore, MD, USA, November 2001
27. st IEEE VLSI Test Symp. (VTS 2003), Napa Valley, CA, USA, April 2003
28. N. Metropolis, A. Rosenbluth, M. Rosenbluth, A. Teller, E. Teller: Equation of State Calculations by Fast Computing Machines; J. Chem. Phys., 21, 1953, pp. 1087-1092
29. J. Rajski, J. et al.: Embedded Deterministic Test for Low Cost Manufacturing Test; Proc. IEEE Int. Test Conf., Baltimore, MD, USA October 2002, pp. 301-310
30. nd Edition, 2000
31. N. A. Touba and E. J. McCluskey: Altering a Pseudo-Random Bit Sequence for Scan-Based BIST; Proc. IEEE Int. Test Conf., Washington, DC, USA, 1996, pp. 167-175
32. E. H. Volkerink, A. Khoche, S. Mitra: Packet-based Input Test Data Compression Techniques; Proc. IEEE Int. Test Conf.; Baltimore, MD, USA October 2002, pp. 154-163
33. F. G. Wolff, C. Papachristou: Multiscan-based Test Compression and Hardware Decompression Using LZ77; Proc. IEEE Int. Test Conf., Baltimore, MD, USA, October 2002, pp. 331-339
34. H.-J. Wunderlich, G. Kiefer: Bit-Flipping BIST; Proc. ACM/IEEE Int. Conf. on CAD-96 (ICCAD96), San Jose, CA, USA, November 1996, pp. 337-343
35. T. Yamaguchi, M. Tilgner, M. Ishida, D. S. Ha: An Efficient Method for Compressing Test Data; Proc. IEEE Int. Test Conf., Washington, DC, USA, 1997, pp. 79-88
36. Y. Zorian: Testing the monster chip; IEEE Spectrum, July 1999, pp. 54-60