Multiscan-based test compression and hardware decompression using LZ77

IEEE International Test Conference (TC)

Volumn , Issue , 2002, Pages 331-339

  Wolff, Francis G ^a   Papachristou, Chris ^a  

^a Case Western Reserve University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; AUTOMATIC TESTING; COMPUTER AIDED DESIGN; COMPUTER AIDED SOFTWARE ENGINEERING; DATA COMPRESSION; ENCODING (SYMBOLS); STATISTICAL METHODS; VECTORS; VLSI CIRCUITS;

AUTOMATIC TEST PATTERN GENERATOR; HARDWARE DECOMPRESSION; TEST COMPRESSION;

INTEGRATED CIRCUIT TESTING;

EID: 0036456025     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (23)

1. C. Barnhart, V. Brunkhorst, F. Distler, O. Farnsworth, B. Keller, and B. Koeneman. Opmisr: The foundation for compressed atpg vectors. In Proc. Int'l Test Conf., pages 748-757, 2001.
2. F. Brglez, D. Bryan, and K. Kozminski. Combinatorial profiles of sequential benchmark circuits. In Proc. Int'l Symp. on Circuits and Systems, pages 1129-1234, 1989.
3. A. Chandra and K. Chakrabarty. System-on-a-chip test-data compression and decompression architecture based on golomb codes. IEEE Trans. on CAD/ICAS, (3):355-368, March 2001.
4. A. Chandra and K. Chakrabarty. Reduction of soc test data volume, scan power and testing time using alternating run-length codes. In Proc. Design Automation Conference, pages 673-678, June 2002.
5. P. Deutsch. DEFLATE Compressed Data Format Specification version 1.3, RFC 1951, http://www.w3.org/Graphics/PNG/RFC-1951, May 1996.
6. R. Dorsch and H.-J. Wunderlich. Tailoring atpg for embedded testing. In Int'l Test Conf., pages 530-537, 2001.
7. B. T. et al. PNG (Portable Network Graphics) specification version. http://www.w3.org/Graphics/PNG, 1996.
8. J. A. Gasbarro and M. A. Horowitz. A single-chip, functional tester for vlsi circuits. In Int'l Solid-State Conference, pages 84-85,268, 1990.
9. H. Ichihara, A. Ogawa, T. Inoue, and A. Tamura. Dynamic test compression using statistical coding. In Proc. of Asian Test Symposium, pages 143-148, 2001.
10. V. Iyengar, K. Chakrabarty, and B. T. Murray. Deterministic built-in pattern generation for sequential circuits. JETTA, 15:97-115, October 1999.
11. A. Jas, J. Ghosh-Dastidar, and N. A. Touba. Scan vector compression/decompression using statistical coding. In Proc. VLSI Test Symp., pages 114-120. April 1999.
12. A. Jas and N. Touba. Test vector decompression via cyclical scan chains. In Proc. Int'l Test Conf., pages 458-464, 1998.
13. S. Kajihara and K. Miyase. On identifying don't care inputs of test patterns for combinational circuits. In Proc. Int'l Conf. Computer-Aided Design, pages 364-369, 2001.
14. A. Khoche, E. H. Volkerink, J. Rivoir, and S. Mitra Test vector compression using eda-ate synergies. In Proc. VLSI Test Symp., pages 97-102, 2002.
15. B. Koeneman, C. Barnhart, B. Keller, T. Snethen, O. Farnsworth, and D. Wheater. A smartbist variant with guaranteed encoding. In Proc. Asian Test Conf., pages 325-330, 2001.
16. K. Loudon. Mastering Algorithms with C. O'Reilly, 1999.
17. M. Nelson and J. L. Gailly. The Data Compression Book. M & T Books, New York, 1996.
18. J. Rajski. Dft for high-quality low cost manufacturing test. In Asian Test Symp., pages 3-8, 2001.
19. E. H. Volkerink, A. Khoche, J. Rivoir, and K. D. Hilliges. Test economics for multi-site test with modern cost reduction techniques. In Proc. VLSI Test Symp., pages 411-416, 2002.
20. T. A. Welch. A technique for high-performance data compression. IEEE Computer, 17(6):8-19, June 1984.
21. J. Ziv and A. Lempel. A universal algorithm for sequential data compression. IEEE Trans. on Information Theory, 23(3):337-343, May 1977.
22. J. Ziv and A. Lempel. Compression of individual sequences via variable rate coding. IEEE Trans. on Information Theory, 24(5):530-536, 1978.
23. Y. Zorian, E. J. Marinissen, and S. Dey. Testing embedded-core-based system chips. Computer, 32(6):52-60, 1999.