Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2001, Pages 278-279

  Bowman, Keith A ^a,b   Duvall, Steven G ^b,c   Meindl, James D ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b INTEL CORPORATION   (United States)

^c Intel Australia Pty Ltd   (Australia)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; FREQUENCIES; MATHEMATICAL MODELS; NORMAL DISTRIBUTION; STATISTICAL METHODS; WSI CIRCUITS;

CLOCK FREQUENCIES; DIE-TO-DIE PARAMETERS; WITHIN-DIE PARAMETERS;

MICROPROCESSOR CHIPS;

EID: 0035060746     PISSN: 01936530     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.982424     Document Type: Article

References (4)

1. Statistical circuit modeling and optimization
2. The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits
3. Supply and threshold voltage optimization for low power design
4. Impact of extrinsic and intrinsic parameter fluctuations on CMOS circuit performance